


ARM Macro Assembler    Page 1 


    1 00000000         ;*******************************************************
                       *************************************************
    2 00000000         ;                                               uC/OS-II
                       
    3 00000000         ;                                         The Real-Time 
                       Kernel
    4 00000000         ;
    5 00000000         ;                               (c) Copyright 1992-2006,
                        Micrium, Weston, FL
    6 00000000         ;                                          All Rights Re
                       served
    7 00000000         ;
    8 00000000         ;                                           Generic ARM 
                       Port
    9 00000000         ;
   10 00000000         ; File      : OS_CPU_A.S
   11 00000000         ; Version   : V2.86
   12 00000000         ; By        : Jean J. Labrosse
   13 00000000         ;
   14 00000000         ; For       : ARMv7M Cortex-M0
   15 00000000         ; Mode      : Thumb & some Thumb2
   16 00000000         ; Toolchain : RealView Development Suite
   17 00000000         ;             RealView Microcontroller Development Kit (
                       MDK)
   18 00000000         ;             ARM Developer Suite (ADS)
   19 00000000         ;             Keil uVision
   20 00000000         ;*******************************************************
                       *************************************************
   21 00000000         
   22 00000000         ;*******************************************************
                       *************************************************
   23 00000000         ;                                           PUBLIC FUNCT
                       IONS
   24 00000000         ;*******************************************************
                       *************************************************
   25 00000000         
   26 00000000                 EXTERN           OSRunning   ; External referenc
                                                            es
   27 00000000                 EXTERN           OSPrioCur
   28 00000000                 EXTERN           OSPrioHighRdy
   29 00000000                 EXTERN           OSTCBCur
   30 00000000                 EXTERN           OSTCBHighRdy
   31 00000000                 EXTERN           OSIntNesting
   32 00000000                 EXTERN           OSIntExit
   33 00000000                 EXTERN           OSTaskSwHook
   34 00000000         
   35 00000000         
   36 00000000                 EXPORT           OS_CPU_SR_Save ; Functions decl
                                                            ared in this file
   37 00000000                 EXPORT           OS_CPU_SR_Restore
   38 00000000                 EXPORT           OSStartHighRdy
   39 00000000                 EXPORT           OSCtxSw
   40 00000000                 EXPORT           OSIntCtxSw
   41 00000000                 EXPORT           OS_CPU_PendSVHandler
   42 00000000         
   43 00000000         ;*******************************************************
                       *************************************************
   44 00000000         ;                                                EQUATES
                       



ARM Macro Assembler    Page 2 


   45 00000000         ;*******************************************************
                       *************************************************
   46 00000000         
   47 00000000 E000ED04 
                       NVIC_INT_CTRL
                               EQU              0xE000ED04  ; Interrupt control
                                                             state register.
   48 00000000         ;NVIC_SYSPRI14   EQU     0xE000ED22                     
                                ; System priority register (priority 14).
   49 00000000 E000ED20 
                       NVIC_SCB_SHPR3
                               EQU              0xE000ED20
   50 00000000         ;NVIC_PENDSV_PRI EQU           0xFF                     
                                ; PendSV priority value (lowest).
   51 00000000 00FF0000 
                       NVIC_PENDSV_PRI
                               EQU              0x00FF0000
   52 00000000 10000000 
                       NVIC_PENDSVSET
                               EQU              0x10000000  ; Value to trigger 
                                                            PendSV exception.
   53 00000000         
   54 00000000         
   55 00000000         
   56 00000000         
   57 00000000         ;*******************************************************
                       *************************************************
   58 00000000         ;                                      CODE GENERATION D
                       IRECTIVES
   59 00000000         ;*******************************************************
                       *************************************************
   60 00000000         
   61 00000000                 AREA             |.text|, CODE, READONLY, ALIGN=
2
   62 00000000                 THUMB
   63 00000000                 REQUIRE8
   64 00000000                 PRESERVE8
   65 00000000         
   66 00000000         ;*******************************************************
                       *************************************************
   67 00000000         ;                                   CRITICAL SECTION MET
                       HOD 3 FUNCTIONS
   68 00000000         ;
   69 00000000         ; Description: Disable/Enable interrupts by preserving t
                       he state of interrupts.  Generally speaking you
   70 00000000         ;              would store the state of the interrupt di
                       sable flag in the local variable 'cpu_sr' and then
   71 00000000         ;              disable interrupts.  'cpu_sr' is allocate
                       d in all of uC/OS-II's functions that need to
   72 00000000         ;              disable interrupts.  You would restore th
                       e interrupt disable state by copying back 'cpu_sr'
   73 00000000         ;              into the CPU's status register.
   74 00000000         ;
   75 00000000         ; Prototypes :     OS_CPU_SR  OS_CPU_SR_Save(void);
   76 00000000         ;                  void       OS_CPU_SR_Restore(OS_CPU_S
                       R cpu_sr);
   77 00000000         ;
   78 00000000         ;
   79 00000000         ; Note(s)    : 1) These functions are used in general li



ARM Macro Assembler    Page 3 


                       ke this:
   80 00000000         ;
   81 00000000         ;                 void Task (void *p_arg)
   82 00000000         ;                 {
   83 00000000         ;                 #if OS_CRITICAL_METHOD == 3          /
                       * Allocate storage for CPU status register */
   84 00000000         ;                     OS_CPU_SR  cpu_sr;
   85 00000000         ;                 #endif
   86 00000000         ;
   87 00000000         ;                          :
   88 00000000         ;                          :
   89 00000000         ;                     OS_ENTER_CRITICAL();             /
                       * cpu_sr = OS_CPU_SaveSR();                */
   90 00000000         ;                          :
   91 00000000         ;                          :
   92 00000000         ;                     OS_EXIT_CRITICAL();              /
                       * OS_CPU_RestoreSR(cpu_sr);                */
   93 00000000         ;                          :
   94 00000000         ;                          :
   95 00000000         ;                 }
   96 00000000         ;*******************************************************
                       *************************************************
   97 00000000         
   98 00000000         OS_CPU_SR_Save
   99 00000000 F3EF 8010       MRS              R0, PRIMASK ; Set prio int mask
                                                             to mask all (excep
                                                            t faults)
  100 00000004 B672            CPSID            I
  101 00000006 4770            BX               LR
  102 00000008         
  103 00000008         OS_CPU_SR_Restore
  104 00000008 F380 8810       MSR              PRIMASK, R0
  105 0000000C 4770            BX               LR
  106 0000000E         
  107 0000000E         ;*******************************************************
                       *************************************************
  108 0000000E         ;                                          START MULTITA
                       SKING
  109 0000000E         ;                                       void OSStartHigh
                       Rdy(void)
  110 0000000E         ;
  111 0000000E         ; Note(s) : 1) This function triggers a PendSV exception
                        (essentially, causes a context switch) to cause
  112 0000000E         ;              the first task to start.
  113 0000000E         ;
  114 0000000E         ;           2) OSStartHighRdy() MUST:
  115 0000000E         ;              a) Setup PendSV exception priority to low
                       est;
  116 0000000E         ;              b) Set initial PSP to 0, to tell context 
                       switcher this is first run;
  117 0000000E         ;              c) Set OSRunning to TRUE;
  118 0000000E         ;              d) Trigger PendSV exception;
  119 0000000E         ;              e) Enable interrupts (tasks will run with
                        interrupts enabled).
  120 0000000E         ;*******************************************************
                       *************************************************
  121 0000000E         
  122 0000000E         OSStartHighRdy
  123 0000000E         ;LDR     R0, =NVIC_SYSPRI14                             



ARM Macro Assembler    Page 4 


                            ; Set the PendSV exception priority
  124 0000000E         ;LDR     R1, =NVIC_PENDSV_PRI
  125 0000000E         ;STRB    R1, [R0]
  126 0000000E 4823            ldr              r0, =NVIC_SCB_SHPR3
  127 00000010 6801            ldr              r1, [r0]
  128 00000012 4A23            ldr              r2, =NVIC_PENDSV_PRI
  129 00000014 4311            orrs             r1, r1, r2
  130 00000016 6001            str              r1, [r0]
  131 00000018         
  132 00000018 2000            MOVS             R0, #0      ; Set the PSP to 0 
                                                            for initial context
                                                             switch call
  133 0000001A F380 8809       MSR              PSP, R0
  134 0000001E         
  135 0000001E 4821            LDR              R0, =OSRunning 
                                                            ; OSRunning = TRUE
  136 00000020 2101            MOVS             R1, #1
  137 00000022 7001            STRB             R1, [R0]
  138 00000024         
  139 00000024 4820            LDR              R0, =NVIC_INT_CTRL ; Trigger th
                                                            e PendSV exception 
                                                            (causes context swi
                                                            tch)
  140 00000026 4921            LDR              R1, =NVIC_PENDSVSET
  141 00000028 6001            STR              R1, [R0]
  142 0000002A         
  143 0000002A B662            CPSIE            I           ; Enable interrupts
                                                             at processor level
                                                            
  144 0000002C         
  145 0000002C         OSStartHang
  146 0000002C E7FE            B                OSStartHang ; Should never get 
                                                            here
  147 0000002E         
  148 0000002E         
  149 0000002E         ;*******************************************************
                       *************************************************
  150 0000002E         ;                               PERFORM A CONTEXT SWITCH
                        (From task level)
  151 0000002E         ;                                           void OSCtxSw
                       (void)
  152 0000002E         ;
  153 0000002E         ; Note(s) : 1) OSCtxSw() is called when OS wants to perf
                       orm a task context switch.  This function
  154 0000002E         ;              triggers the PendSV exception which is wh
                       ere the real work is done.
  155 0000002E         ;*******************************************************
                       *************************************************
  156 0000002E         
  157 0000002E         OSCtxSw
  158 0000002E 481E            LDR              R0, =NVIC_INT_CTRL ; Trigger th
                                                            e PendSV exception 
                                                            (causes context swi
                                                            tch)
  159 00000030 491E            LDR              R1, =NVIC_PENDSVSET
  160 00000032 6001            STR              R1, [R0]
  161 00000034 4770            BX               LR
  162 00000036         
  163 00000036         ;*******************************************************



ARM Macro Assembler    Page 5 


                       *************************************************
  164 00000036         ;                             PERFORM A CONTEXT SWITCH (
                       From interrupt level)
  165 00000036         ;                                         void OSIntCtxS
                       w(void)
  166 00000036         ;
  167 00000036         ; Notes:    1) OSIntCtxSw() is called by OSIntExit() whe
                       n it determines a context switch is needed as
  168 00000036         ;              the result of an interrupt.  This functio
                       n simply triggers a PendSV exception which will
  169 00000036         ;              be handled when there are no more interru
                       pts active and interrupts are enabled.
  170 00000036         ;*******************************************************
                       *************************************************
  171 00000036         
  172 00000036         OSIntCtxSw
  173 00000036 481C            LDR              R0, =NVIC_INT_CTRL ; Trigger th
                                                            e PendSV exception 
                                                            (causes context swi
                                                            tch)
  174 00000038 491C            LDR              R1, =NVIC_PENDSVSET
  175 0000003A 6001            STR              R1, [R0]
  176 0000003C 4770            BX               LR
  177 0000003E         
  178 0000003E         ;*******************************************************
                       *************************************************
  179 0000003E         ;                                         HANDLE PendSV 
                       EXCEPTION
  180 0000003E         ;                                     void OS_CPU_PendSV
                       Handler(void)
  181 0000003E         ;
  182 0000003E         ; Note(s) : 1) PendSV is used to cause a context switch.
                         This is a recommended method for performing
  183 0000003E         ;              context switches with Cortex-M3.  This is
                        because the Cortex-M3 auto-saves half of the
  184 0000003E         ;              processor context on any exception, and r
                       estores same on return from exception.  So only
  185 0000003E         ;              saving of R4-R11 is required and fixing u
                       p the stack pointers.  Using the PendSV exception
  186 0000003E         ;              this way means that context saving and re
                       storing is identical whether it is initiated from
  187 0000003E         ;              a thread or occurs due to an interrupt or
                        exception.
  188 0000003E         ;
  189 0000003E         ;           2) Pseudo-code is:
  190 0000003E         ;              a) Get the process SP, if 0 then skip (go
                       to d) the saving part (first context switch);
  191 0000003E         ;              b) Save remaining regs r4-r11 on process 
                       stack;
  192 0000003E         ;              c) Save the process SP in its TCB, OSTCBC
                       ur->OSTCBStkPtr = SP;
  193 0000003E         ;              d) Call OSTaskSwHook();
  194 0000003E         ;              e) Get current high priority, OSPrioCur =
                        OSPrioHighRdy;
  195 0000003E         ;              f) Get current ready thread TCB, OSTCBCur
                        = OSTCBHighRdy;
  196 0000003E         ;              g) Get new process SP from TCB, SP = OSTC
                       BHighRdy->OSTCBStkPtr;
  197 0000003E         ;              h) Restore R4-R11 from new process stack;



ARM Macro Assembler    Page 6 


                       
  198 0000003E         ;              i) Perform exception return which will re
                       store remaining context.
  199 0000003E         ;
  200 0000003E         ;           3) On entry into PendSV handler:
  201 0000003E         ;              a) The following have been saved on the p
                       rocess stack (by processor):
  202 0000003E         ;                 xPSR, PC, LR, R12, R0-R3
  203 0000003E         ;              b) Processor mode is switched to Handler 
                       mode (from Thread mode)
  204 0000003E         ;              c) Stack is Main stack (switched from Pro
                       cess stack)
  205 0000003E         ;              d) OSTCBCur      points to the OS_TCB of 
                       the task to suspend
  206 0000003E         ;                 OSTCBHighRdy  points to the OS_TCB of 
                       the task to resume
  207 0000003E         ;
  208 0000003E         ;           4) Since PendSV is set to lowest priority in
                        the system (by OSStartHighRdy() above), we
  209 0000003E         ;              know that it will only be run when no oth
                       er exception or interrupt is active, and
  210 0000003E         ;              therefore safe to assume that context bei
                       ng switched out was using the process stack (PSP).
  211 0000003E         ;*******************************************************
                       *************************************************
  212 0000003E         
  213 0000003E         OS_CPU_PendSVHandler
  214 0000003E B672            CPSID            I           ; Prevent interrupt
                                                            ion during context 
                                                            switch
  215 00000040 F3EF 8009       MRS              R0, PSP     ; PSP is process st
                                                            ack pointer
  216 00000044         ;CBZ     R0, OS_CPU_PendSVHandler_nosave                
                            ; Skip register save the first time
  217 00000044 2800            cmp              r0, #0
  218 00000046 D00A            beq              OS_CPU_PendSVHandler_nosave
  219 00000048         
  220 00000048 3820            SUBS             R0, R0, #0x20 ; Save remaining 
                                                            regs r4-11 on proce
                                                            ss stack
  221 0000004A         ;STM     R0, {R4-R11}
  222 0000004A C0F0            stm              r0!, {r4-r7}
  223 0000004C 4641            mov              r1, r8
  224 0000004E 464A            mov              r2, r9
  225 00000050 4653            mov              r3, r10
  226 00000052 465C            mov              r4, r11
  227 00000054 C01E            stm              r0!, {r1-r4}
  228 00000056 3820            subs             r0, r0, #0x20
  229 00000058         
  230 00000058 4915            LDR              R1, =OSTCBCur ; OSTCBCur->OSTCB
                                                            StkPtr = SP;
  231 0000005A 6809            LDR              R1, [R1]
  232 0000005C 6008            STR              R0, [R1]    ; R0 is SP of proce
                                                            ss being switched o
                                                            ut
  233 0000005E         
  234 0000005E         ; At this point, entire context of process has been save
                       d
  235 0000005E         OS_CPU_PendSVHandler_nosave



ARM Macro Assembler    Page 7 


  236 0000005E         ;PUSH    {R14}                                          
                            ; Save LR exc_return value
  237 0000005E         ;LDR     R0, =OSTaskSwHook                              
                            ; OSTaskSwHook();
  238 0000005E         ;BLX     R0
  239 0000005E         ;POP     {R14}
  240 0000005E 4670            mov              r0, lr
  241 00000060 B401            push             {r0}
  242 00000062 4814            ldr              r0, =OSTaskSwHook
  243 00000064 4780            blx              r0
  244 00000066 BC01            pop              {r0}
  245 00000068 4686            mov              lr, r0
  246 0000006A         
  247 0000006A 4813            LDR              R0, =OSPrioCur ; OSPrioCur = OS
                                                            PrioHighRdy;
  248 0000006C 4913            LDR              R1, =OSPrioHighRdy
  249 0000006E 780A            LDRB             R2, [R1]
  250 00000070 7002            STRB             R2, [R0]
  251 00000072         
  252 00000072 480F            LDR              R0, =OSTCBCur ; OSTCBCur  = OST
                                                            CBHighRdy;
  253 00000074 4912            LDR              R1, =OSTCBHighRdy
  254 00000076 680A            LDR              R2, [R1]
  255 00000078 6002            STR              R2, [R0]
  256 0000007A         
  257 0000007A 6810            LDR              R0, [R2]    ; R0 is new process
                                                             SP; SP = OSTCBHigh
                                                            Rdy->OSTCBStkPtr;
  258 0000007C         ;LDM     R0, {R4-R11}                                   
                            ; Restore r4-11 from new process stack
  259 0000007C C8F0            ldm              r0!, {r4-r7}
  260 0000007E C80E            ldm              r0!, {r1-r3}
  261 00000080 4688            mov              r8, r1
  262 00000082 4691            mov              r9, r2
  263 00000084 469A            mov              r10, r3
  264 00000086 C802            ldm              r0!, {r1}
  265 00000088 468B            mov              r11, r1
  266 0000008A         
  267 0000008A         ;ADDS    R0, R0, #0x20
  268 0000008A F380 8809       MSR              PSP, R0     ; Load PSP with new
                                                             process SP
  269 0000008E         ;ORR     LR, LR, #0x04                                  
                            ; Ensure exception return uses process stack
  270 0000008E 4670            mov              r0, lr
  271 00000090 2104            movs             r1, #0x04
  272 00000092 4308            orrs             r0, r0, r1
  273 00000094 4686            mov              lr, r0
  274 00000096 B662            CPSIE            I
  275 00000098 4770            BX               LR          ; Exception return 
                                                            will restore remain
                                                            ing context
  276 0000009A         
  277 0000009A E7FE            b                .
  278 0000009C         
  279 0000009C                 END
              E000ED20 
              00FF0000 
              00000000 
              E000ED04 



ARM Macro Assembler    Page 8 


              10000000 
              00000000 
              00000000 
              00000000 
              00000000 
              00000000 
Command Line: --debug --xref --cpu=Cortex-M0 --apcs=interwork --depend=.\output
\os_cpu_a.d -o.\output\os_cpu_a.o -IC:\Keil\ARM\INC -IC:\Keil\ARM\INC\NXP\LPC11
xx --predefine="__MICROLIB SETA 1" --list=.\listing\os_cpu_a.lst ..\uCOS-II_V29
1\CPU\os_cpu_a.s



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.text 00000000

Symbol: .text
   Definitions
      At line 61 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      None
Comment: .text unused
OSCtxSw 0000002E

Symbol: OSCtxSw
   Definitions
      At line 157 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 39 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSCtxSw used once
OSIntCtxSw 00000036

Symbol: OSIntCtxSw
   Definitions
      At line 172 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 40 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSIntCtxSw used once
OSStartHang 0000002C

Symbol: OSStartHang
   Definitions
      At line 145 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 146 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSStartHang used once
OSStartHighRdy 0000000E

Symbol: OSStartHighRdy
   Definitions
      At line 122 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 38 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSStartHighRdy used once
OS_CPU_PendSVHandler 0000003E

Symbol: OS_CPU_PendSVHandler
   Definitions
      At line 213 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 41 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OS_CPU_PendSVHandler used once
OS_CPU_PendSVHandler_nosave 0000005E

Symbol: OS_CPU_PendSVHandler_nosave
   Definitions
      At line 235 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 218 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OS_CPU_PendSVHandler_nosave used once
OS_CPU_SR_Restore 00000008

Symbol: OS_CPU_SR_Restore



ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Relocatable symbols

   Definitions
      At line 103 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 37 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OS_CPU_SR_Restore used once
OS_CPU_SR_Save 00000000

Symbol: OS_CPU_SR_Save
   Definitions
      At line 98 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 36 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OS_CPU_SR_Save used once
9 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Absolute symbols

NVIC_INT_CTRL E000ED04

Symbol: NVIC_INT_CTRL
   Definitions
      At line 47 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 139 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
      At line 158 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
      At line 173 in file ..\uCOS-II_V291\CPU\os_cpu_a.s

NVIC_PENDSVSET 10000000

Symbol: NVIC_PENDSVSET
   Definitions
      At line 52 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 140 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
      At line 159 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
      At line 174 in file ..\uCOS-II_V291\CPU\os_cpu_a.s

NVIC_PENDSV_PRI 00FF0000

Symbol: NVIC_PENDSV_PRI
   Definitions
      At line 51 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 128 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: NVIC_PENDSV_PRI used once
NVIC_SCB_SHPR3 E000ED20

Symbol: NVIC_SCB_SHPR3
   Definitions
      At line 49 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 126 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: NVIC_SCB_SHPR3 used once
4 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
External symbols

OSIntExit 00000000

Symbol: OSIntExit
   Definitions
      At line 32 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      None
Comment: OSIntExit unused
OSIntNesting 00000000

Symbol: OSIntNesting
   Definitions
      At line 31 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      None
Comment: OSIntNesting unused
OSPrioCur 00000000

Symbol: OSPrioCur
   Definitions
      At line 27 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 247 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSPrioCur used once
OSPrioHighRdy 00000000

Symbol: OSPrioHighRdy
   Definitions
      At line 28 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 248 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSPrioHighRdy used once
OSRunning 00000000

Symbol: OSRunning
   Definitions
      At line 26 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 135 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSRunning used once
OSTCBCur 00000000

Symbol: OSTCBCur
   Definitions
      At line 29 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 230 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
      At line 252 in file ..\uCOS-II_V291\CPU\os_cpu_a.s

OSTCBHighRdy 00000000

Symbol: OSTCBHighRdy
   Definitions
      At line 30 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 253 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSTCBHighRdy used once
OSTaskSwHook 00000000




ARM Macro Assembler    Page 2 Alphabetic symbol ordering
External symbols

Symbol: OSTaskSwHook
   Definitions
      At line 33 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
   Uses
      At line 242 in file ..\uCOS-II_V291\CPU\os_cpu_a.s
Comment: OSTaskSwHook used once
8 symbols
347 symbols in table
