


ARM Macro Assembler    Page 1 


    1 00000000         ;/******************************************************
                       ***********************/
    2 00000000         ;/* S3C2440A.S: Startup file for Samsung S3C440A        
                                             */
    3 00000000         ;/******************************************************
                       ***********************/
    4 00000000         ;/* <<< Use Configuration Wizard in Context Menu >>>    
                                             */ 
    5 00000000         ;/******************************************************
                       ***********************/
    6 00000000         ;/* This file is part of the uVision/ARM development too
                       ls.                   */
    7 00000000         ;/* Copyright (c) 2005-2006 Keil Software. All rights re
                       served.               */
    8 00000000         ;/* This software may only be used under the terms of a 
                       valid, current,       */
    9 00000000         ;/* end user licence from KEIL for a compatible version 
                       of KEIL software      */
   10 00000000         ;/* development tools. Nothing else gives you the right 
                       to use this software. */
   11 00000000         ;/******************************************************
                       ***********************/
   12 00000000         
   13 00000000         
   14 00000000         ; *** Startup Code (executed after Reset) ***
   15 00000000         
   16 00000000         
   17 00000000         ; Standard definitions of Mode bits and Interrupt (I & F
                       ) flags in PSRs
   18 00000000         
   19 00000000 00000010 
                       Mode_USR
                               EQU              0x10
   20 00000000 00000011 
                       Mode_FIQ
                               EQU              0x11
   21 00000000 00000012 
                       Mode_IRQ
                               EQU              0x12
   22 00000000 00000013 
                       Mode_SVC
                               EQU              0x13
   23 00000000 00000017 
                       Mode_ABT
                               EQU              0x17
   24 00000000 0000001B 
                       Mode_UND
                               EQU              0x1B
   25 00000000 0000001F 
                       Mode_SYS
                               EQU              0x1F
   26 00000000         
   27 00000000 00000080 
                       I_Bit   EQU              0x80        ; when I bit is set
                                                            , IRQ is disabled
   28 00000000 00000040 
                       F_Bit   EQU              0x40        ; when F bit is set
                                                            , FIQ is disabled
   29 00000000         



ARM Macro Assembler    Page 2 


   30 00000000         ;// <h> Stack Configuration (Stack Sizes in Bytes)
   31 00000000         ;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
   32 00000000         ;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
   33 00000000         ;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
   34 00000000         ;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
   35 00000000         ;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
   36 00000000         ;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
   37 00000000         ;// </h>
   38 00000000         
   39 00000000 00000400 
                       UND_Stack_Size
                               EQU              0x00000400
   40 00000000 00001000 
                       SVC_Stack_Size
                               EQU              0x00001000
   41 00000000 00000400 
                       ABT_Stack_Size
                               EQU              0x00000400
   42 00000000 00001000 
                       FIQ_Stack_Size
                               EQU              0x00001000
   43 00000000 00001000 
                       IRQ_Stack_Size
                               EQU              0x00001000
   44 00000000 00003800 
                       USR_Stack_Size
                               EQU              0x00003800
   45 00000000         
   47 00000000 00007000 
                       Stack_Size
                               EQU              (UND_Stack_Size + SVC_Stack_Siz
e + ABT_Stack_Size +                           FIQ_Stack_Size + IRQ_Stack_Size
 + USR_Stack_Size)
   48 00000000         
   49 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
=3
   50 00000000         Stack_Mem
                               SPACE            Stack_Size
   51 00007000         
   52 00007000 00007000 
                       Stack_Top
                               EQU              Stack_Mem + Stack_Size
   53 00007000         
   54 00007000         
   55 00007000         ;// <h> Heap Configuration
   56 00007000         ;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
   57 00007000         ;// </h>
   58 00007000         
   59 00007000 00004800 
                       Heap_Size
                               EQU              0x00004800
   60 00007000         
   61 00007000                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
3
   62 00000000         Heap_Mem
                               SPACE            Heap_Size
   63 00004800         
   64 00004800         
   65 00004800         ;INT CONFIG



ARM Macro Assembler    Page 3 


   66 00004800 4A000000 
                       INT_BASE
                               EQU              0x4A000000
   67 00004800 00000000 
                       SRCPND_OFS
                               EQU              0x0
   68 00004800 00000008 
                       INTMSK_OFS
                               EQU              0x8
   69 00004800 00000010 
                       INTPND_OFS
                               EQU              0x10
   70 00004800 0000001C 
                       INTSUBMASK_OFS
                               EQU              0x1c
   71 00004800         
   72 00004800 00000001 
                       INT_SETUP
                               EQU              1
   73 00004800 FFFFFFFF 
                       INTMSK_VAL
                               EQU              0xFFFFFFFF
   74 00004800 000007FF 
                       INTSUBMASK_VAL
                               EQU              0X7FF
   75 00004800         
   76 00004800         
   77 00004800         ; Clock Management definitions
   78 00004800 4C000000 
                       CLK_BASE
                               EQU              0x4C000000  ; Clock Base Addres
                                                            s
   79 00004800 00000000 
                       LOCKTIME_OFS
                               EQU              0x00        ; LOCKTIME Offset
   80 00004800 00000004 
                       MPLLCON_OFS
                               EQU              0x04        ; MPLLCON Offset
   81 00004800 00000008 
                       UPLLCON_OFS
                               EQU              0X08        ; UPLLCON Offset
   82 00004800 0000000C 
                       CLKCON_OFS
                               EQU              0x0C        ; CLKCON Offset
   83 00004800 00000010 
                       CLKSLOW_OFS
                               EQU              0x10        ; CLKSLOW Offset
   84 00004800 00000014 
                       CLKDIVN_OFS
                               EQU              0X14        ; CLDKIVN Offset
   85 00004800 00000018 
                       CAMDIVN_OFS
                               EQU              0X18        ; CAMDIVN Offset
   86 00004800         
   87 00004800         
   88 00004800         
   89 00004800         ;// <e> Clock Management
   90 00004800         ;//   <h> MPLL Settings
   91 00004800         ;//   <i> Mpll = (m * Fin) / (p * 2^s)



ARM Macro Assembler    Page 4 


   92 00004800         ;//     <o1.12..19> MDIV: Main divider <0x0-0xFF>
   93 00004800         ;//                 <i> m = MDIV + 8
   94 00004800         ;//     <o1.4..9>   PDIV: Pre-divider  <0x0-0x3F>
   95 00004800         ;//                 <i> p = PDIV + 2
   96 00004800         ;//     <o1.0..1>   SDIV: Post Divider <0x0-0x03>
   97 00004800         ;//                 <i> s = SDIV 
   98 00004800         ;//   </h>
   99 00004800         ;//   <h> UPLL Settings
  100 00004800         ;//   <i> Upll = ( m * Fin) / (p * 2^s),Uclk must be 48M
                       HZ to USB device 
  101 00004800         ;//     <o2.12..19> MDIV: Main divider <0x1-0xF8>
  102 00004800         ;//                 <i> m = MDIV + 8,if Fin=12MHZ MDIV c
                       ould be 0x38   
  103 00004800         ;//     <o2.4..9>   PDIV: Pre-divider  <0x1-0x3E>
  104 00004800         ;//                 <i> p = PDIV + 2,if Fin=12MHZ PDIV c
                       ould be 0x2
  105 00004800         ;//     <o2.0..1>   SDIV: Post Divider <0x0-0x03>
  106 00004800         ;//                 <i> s = SDIV ,if Fin=12MHZ SDIV coul
                       d be 0x2
  107 00004800         ;//   </h>
  108 00004800         ;//   <h>LOCK TIME 
  109 00004800         ;//      <o5.0..11>  LTIME CNT: MPLL Lock Time Count  <0
                       x0-0xFFF>
  110 00004800         ;//      <o5.12..23>  LTIME CNT: UPLL Lock Time Count  <
                       0x0-0xFFF>
  111 00004800         ;//   </h>
  112 00004800         ;//   <h> Master Clock
  113 00004800         ;//   <i> PLL Clock:  FCLK = FMPLL
  114 00004800         ;//   <i> Slow Clock: FCLK = Fin / (2 * SLOW_VAL), SLOW_
                       VAL > 0
  115 00004800         ;//   <i> Slow Clock: FCLK = Fin, SLOW_VAL = 0
  116 00004800         ;//     <o4.7>      UCLK_ON: UCLK ON
  117 00004800         ;//                 <i> 0: UCLK ON(UPLL is also turned o
                       n) 1: UCLK OFF (UPLL is also turned off)   
  118 00004800         ;//     <o4.5>      MPLL_OFF: Turn off PLL
  119 00004800         ;//                 <i> 0: Turn on PLL.After PLL stabili
                       zation time (minimum 300us), SLOW_BIT can be cleared to 
                       0. 1: Turn off PLL. PLL is turned off only when SLOW_BIT
                        is 1.
  120 00004800         ;//     <o4.4>      SLOW_BIT: Slow Clock
  121 00004800         ;//     <o4.0..2>   SLOW_VAL: Slow Clock divider    <0x0
                       -0x7>
  122 00004800         ;//   </h>
  123 00004800         ;//   <h> CLOCK DIVIDER CONTROL
  124 00004800         ;//     <o6.1>   HDIVN                            
  125 00004800         ;//                  <i> 0: HCLK = FCLK/1, 01 : HCLK = F
                       CLK/2
  126 00004800         ;//     <o6.0>      PDIVN
  127 00004800         ;//                  <i> 0: PCLK has the clock same as t
                       he HCLK/1,1: PCLK has the clock same as the HCLK/2
  128 00004800         ;//    </h>
  129 00004800         ;//  <h> Clock Generation
  130 00004800         ;//     <o3.18>     SPI          <0=> Disable  <1=> Enab
                       le
  131 00004800         ;//     <o3.17>     IIS          <0=> Disable  <1=> Enab
                       le
  132 00004800         ;//     <o3.16>     IIC          <0=> Disable  <1=> Enab
                       le
  133 00004800         ;//     <o3.15>     ADC          <0=> Disable  <1=> Enab



ARM Macro Assembler    Page 5 


                       le
  134 00004800         ;//     <o3.14>     RTC          <0=> Disable  <1=> Enab
                       le
  135 00004800         ;//     <o3.13>     GPIO         <0=> Disable  <1=> Enab
                       le
  136 00004800         ;//     <o3.12>     UART2        <0=> Disable  <1=> Enab
                       le
  137 00004800         ;//     <o3.11>     UART1        <0=> Disable  <1=> Enab
                       le
  138 00004800         ;//     <o3.10>     UART0        <0=> Disable  <1=> Enab
                       le
  139 00004800         ;//     <o3.9>      SDI          <0=> Disable  <1=> Enab
                       le
  140 00004800         ;//     <o3.8>      PWMTIMER     <0=> Disable  <1=> Enab
                       le
  141 00004800         ;//     <o3.7>      USB device   <0=> Disable  <1=> Enab
                       le
  142 00004800         ;//     <o3.6>      USB host     <0=> Disable  <1=> Enab
                       le
  143 00004800         ;//     <o3.5>      LCDC         <0=> Disable  <1=> Enab
                       le
  144 00004800         ;//     <o3.4>      NAND FLASH Controller       <0=> Dis
                       able  <1=> Enable
  145 00004800         ;//     <o3.3>      POWER-OFF    <0=> Disable  <1=> Enab
                       le
  146 00004800         ;//     <o3.2>      IDLE BIT     <0=> Disable  <1=> Enab
                       le
  147 00004800         ;//     <O3.0>      SM_BIT       <0=> Disable  <1=> Enab
                       le
  148 00004800         ;//   </h>
  149 00004800         ;// </e>
  150 00004800 00000000 
                       CLK_SETUP
                               EQU              0
  151 00004800 0005C042 
                       MPLLCON_Val
                               EQU              0x0005C042
  152 00004800 00028080 
                       UPLLCON_Val
                               EQU              0x00028080
  153 00004800 0007FFF0 
                       CLKCON_Val
                               EQU              0x0007FFF0
  154 00004800 00000004 
                       CLKSLOW_Val
                               EQU              0x00000004
  155 00004800 00FFFFFF 
                       LOCKTIME_Val
                               EQU              0x00FFFFFF
  156 00004800 00000003 
                       CLKDIVN_Val
                               EQU              0X00000003
  157 00004800         
  158 00004800         
  159 00004800         
  160 00004800         ;Interrupt  definitions
  161 00004800 4A000014 
                       INTOFFSET
                               EQU              0X4A000014  ;Address of Interru



ARM Macro Assembler    Page 6 


                                                            pt offset Register
  162 00004800         
  163 00004800         ;//<e> Interrupt Vector Table
  164 00004800         ;//  <o1.0..31> Interrupt Vector address     <0x20-0x3ff
                       fff78>
  165 00004800         ;//            <i> You could define Interuupt Vctor Tabl
                       e address.  
  166 00004800         ;//            <i> The Interrupt Vector Table address mu
                       st be word aligned adress. 
  167 00004800         ;//</e>  
  168 00004800 00000001 
                       IntVT_SETUP
                               EQU              1
  169 00004800 33FFFF20 
                       IntVTAddress
                               EQU              0x33FFFF20
  170 00004800         
  171 00004800         ; Watchdog Timer definitions
  172 00004800 53000000 
                       WT_BASE EQU              0x53000000  ; WT Base Address
  173 00004800 00000000 
                       WTCON_OFS
                               EQU              0x00        ; WTCON Offset
  174 00004800 00000004 
                       WTDAT_OFS
                               EQU              0x04        ; WTDAT Offset
  175 00004800 00000008 
                       WTCNT_OFS
                               EQU              0x08        ; WTCNT Offset
  176 00004800         
  177 00004800         ;// <e> Watchdog Timer
  178 00004800         ;//   <o1.5>      Watchdog Timer Enable/Disable
  179 00004800         ;//   <o1.0>      Reset Enable/Disable
  180 00004800         ;//   <o1.2>      Interrupt Enable/Disable
  181 00004800         ;//   <o1.3..4>   Clock Select  
  182 00004800         ;//               <0=> 1/16  <1=> 1/32  <2=> 1/64  <3=> 
                       1/128
  183 00004800         ;//               <i> Clock Division Factor
  184 00004800         ;//   <o1.8..15>  Prescaler Value <0x0-0xFF>
  185 00004800         ;//   <o2.0..15>  Time-out Value  <0x0-0xFFFF>
  186 00004800         ;// </e>
  187 00004800 00000001 
                       WT_SETUP
                               EQU              1
  188 00004800 00000000 
                       WTCON_Val
                               EQU              0x00000000
  189 00004800 00008000 
                       WTDAT_Val
                               EQU              0x00008000
  190 00004800         
  191 00004800         
  192 00004800         ; Memory Controller definitions
  193 00004800 48000000 
                       MC_BASE EQU              0x48000000  ; Memory Controller
                                                             Base Address
  194 00004800         
  195 00004800         ;// <e> Memory Controller
  196 00004800 00000001 



ARM Macro Assembler    Page 7 


                       MC_SETUP
                               EQU              1
  197 00004800         
  198 00004800         ;//   <h> Bank 0
  199 00004800         ;//     <o0.0..1>   PMC: Page Mode Configuration
  200 00004800         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  201 00004800         ;//     <o0.2..3>   Tpac: Page Mode Access Cycle
  202 00004800         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  203 00004800         ;//     <o0.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  204 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  205 00004800         ;//     <o0.6..7>   Toch: Chip Select Hold on nOE
  206 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  207 00004800         ;//     <o0.8..10>  Tacc: Access Cycle
  208 00004800         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  209 00004800         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  210 00004800         ;//     <o0.11..12> Tcos: Chip Select Set-up nOE
  211 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  212 00004800         ;//     <o0.13..14> Tacs: Address Set-up before nGCSn
  213 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  214 00004800         ;//   </h>
  215 00004800         ;//
  216 00004800         ;//   <h> Bank 1
  217 00004800         ;//     <o8.4..5>   DW: Data Bus Width
  218 00004800         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  219 00004800         ;//     <o8.6>      WS: WAIT Status
  220 00004800         ;//                 <0=> WAIT Disable
  221 00004800         ;//                 <1=> WAIT Enable
  222 00004800         ;//     <o8.7>      ST: SRAM Type
  223 00004800         ;//                 <0=> Not using UB/LB
  224 00004800         ;//                 <1=> Using UB/LB
  225 00004800         ;//     <o1.0..1>   PMC: Page Mode Configuration
  226 00004800         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  227 00004800         ;//     <o1.2..3>   Tpac: Page Mode Access Cycle
  228 00004800         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  229 00004800         ;//     <o1.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  230 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  231 00004800         ;//     <o1.6..7>   Toch: Chip Select Hold on nOE
  232 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  233 00004800         ;//     <o1.8..10>  Tacc: Access Cycle
  234 00004800         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  235 00004800         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  236 00004800         ;//     <o1.11..12> Tcos: Chip Select Set-up nOE



ARM Macro Assembler    Page 8 


  237 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  238 00004800         ;//     <o1.13..14> Tacs: Address Set-up before nGCSn
  239 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  240 00004800         ;//   </h>
  241 00004800         ;//
  242 00004800         ;//   <h> Bank 2
  243 00004800         ;//     <o8.8..9>   DW: Data Bus Width
  244 00004800         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  245 00004800         ;//     <o8.10>     WS: WAIT Status
  246 00004800         ;//                 <0=> WAIT Disable
  247 00004800         ;//                 <1=> WAIT Enable
  248 00004800         ;//     <o8.11>     ST: SRAM Type
  249 00004800         ;//                 <0=> Not using UB/LB
  250 00004800         ;//                 <1=> Using UB/LB
  251 00004800         ;//     <o2.0..1>   PMC: Page Mode Configuration
  252 00004800         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  253 00004800         ;//     <o2.2..3>   Tpac: Page Mode Access Cycle
  254 00004800         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  255 00004800         ;//     <o2.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  256 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  257 00004800         ;//     <o2.6..7>   Toch: Chip Select Hold on nOE
  258 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  259 00004800         ;//     <o2.8..10>  Tacc: Access Cycle
  260 00004800         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  261 00004800         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  262 00004800         ;//     <o2.11..12> Tcos: Chip Select Set-up nOE
  263 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  264 00004800         ;//     <o2.13..14> Tacs: Address Set-up before nGCSn
  265 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  266 00004800         ;//   </h>
  267 00004800         ;//
  268 00004800         ;//   <h> Bank 3
  269 00004800         ;//     <o8.12..13> DW: Data Bus Width
  270 00004800         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  271 00004800         ;//     <o8.14>     WS: WAIT Status
  272 00004800         ;//                 <0=> WAIT Disable
  273 00004800         ;//                 <1=> WAIT Enable
  274 00004800         ;//     <o8.15>     ST: SRAM Type
  275 00004800         ;//                 <0=> Not using UB/LB
  276 00004800         ;//                 <1=> Using UB/LB
  277 00004800         ;//     <o3.0..1>   PMC: Page Mode Configuration
  278 00004800         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  279 00004800         ;//     <o3.2..3>   Tpac: Page Mode Access Cycle
  280 00004800         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks



ARM Macro Assembler    Page 9 


  281 00004800         ;//     <o3.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  282 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  283 00004800         ;//     <o3.6..7>   Toch: Chip Select Hold on nOE
  284 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  285 00004800         ;//     <o3.8..10>  Tacc: Access Cycle
  286 00004800         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  287 00004800         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  288 00004800         ;//     <o3.11..12> Tcos: Chip Select Set-up nOE
  289 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  290 00004800         ;//     <o3.13..14> Tacs: Address Set-up before nGCSn
  291 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  292 00004800         ;//   </h>
  293 00004800         ;//
  294 00004800         ;//   <h> Bank 4
  295 00004800         ;//     <o8.16..17> DW: Data Bus Width
  296 00004800         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  297 00004800         ;//     <o8.18>     WS: WAIT Status
  298 00004800         ;//                 <0=> WAIT Disable
  299 00004800         ;//                 <1=> WAIT Enable
  300 00004800         ;//     <o8.19>     ST: SRAM Type
  301 00004800         ;//                 <0=> Not using UB/LB
  302 00004800         ;//                 <1=> Using UB/LB
  303 00004800         ;//     <o4.0..1>   PMC: Page Mode Configuration
  304 00004800         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  305 00004800         ;//     <o4.2..3>   Tpac: Page Mode Access Cycle
  306 00004800         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  307 00004800         ;//     <o4.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  308 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  309 00004800         ;//     <o4.6..7>   Toch: Chip Select Hold on nOE
  310 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  311 00004800         ;//     <o4.8..10>  Tacc: Access Cycle
  312 00004800         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  313 00004800         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  314 00004800         ;//     <o4.11..12> Tcos: Chip Select Set-up nOE
  315 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  316 00004800         ;//     <o4.13..14> Tacs: Address Set-up before nGCSn
  317 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  318 00004800         ;//   </h>
  319 00004800         ;//
  320 00004800         ;//   <h> Bank 5
  321 00004800         ;//     <o8.20..21> DW: Data Bus Width
  322 00004800         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi



ARM Macro Assembler    Page 10 


                       t  <3=> Rsrvd
  323 00004800         ;//     <o8.22>     WS: WAIT Status
  324 00004800         ;//                 <0=> WAIT Disable
  325 00004800         ;//                 <1=> WAIT Enable
  326 00004800         ;//     <o8.23>     ST: SRAM Type
  327 00004800         ;//                 <0=> Not using UB/LB
  328 00004800         ;//                 <1=> Using UB/LB
  329 00004800         ;//     <o5.0..1>   PMC: Page Mode Configuration
  330 00004800         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  331 00004800         ;//     <o5.2..3>   Tpac: Page Mode Access Cycle
  332 00004800         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  333 00004800         ;//     <o5.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  334 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  335 00004800         ;//     <o5.6..7>   Toch: Chip Select Hold on nOE
  336 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  337 00004800         ;//     <o5.8..10>  Tacc: Access Cycle
  338 00004800         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  339 00004800         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  340 00004800         ;//     <o5.11..12> Tcos: Chip Select Set-up nOE
  341 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  342 00004800         ;//     <o5.13..14> Tacs: Address Set-up before nGCSn
  343 00004800         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  344 00004800         ;//   </h>
  345 00004800         ;//
  346 00004800         ;//   <h> Bank 6
  347 00004800         ;//     <o10.0..2>  BK76MAP: Bank 6/7 Memory Map
  348 00004800         ;//                 <0=> 32M  <1=> 64M <2=> 128M <4=> 2M
                          <5=> 4M   <6=> 8M   <7=> 16M
  349 00004800         ;//     <o8.24..25> DW: Data Bus Width
  350 00004800         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  351 00004800         ;//     <o8.26>     WS: WAIT Status
  352 00004800         ;//                 <0=> WAIT Disable
  353 00004800         ;//                 <1=> WAIT Enable
  354 00004800         ;//     <o8.27>     ST: SRAM Type
  355 00004800         ;//                 <0=> Not using UB/LB
  356 00004800         ;//                 <1=> Using UB/LB
  357 00004800         ;//     <o6.15..16> MT: Memory Type
  358 00004800         ;//                 <0=> ROM or SRAM
  359 00004800         ;//                 <3=> SDRAM
  360 00004800         ;//     <h> ROM or SRAM
  361 00004800         ;//       <o6.0..1>   PMC: Page Mode Configuration
  362 00004800         ;//                   <0=> 1 Data  <1=> 4 Data  <2=> 8 D
                       ata  <3=> 16 Data
  363 00004800         ;//       <o6.2..3>   Tpac: Page Mode Access Cycle
  364 00004800         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  365 00004800         ;//       <o6.4..5>   Tcah: Address Holding Time after n
                       GCSn
  366 00004800         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c



ARM Macro Assembler    Page 11 


                       lks  <3=> 4 clks
  367 00004800         ;//       <o6.6..7>   Toch: Chip Select Hold on nOE
  368 00004800         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  369 00004800         ;//       <o6.8..10>  Tacc: Access Cycle
  370 00004800         ;//                   <0=> 1 clk   <1=> 2 clks  <2=> 3 c
                       lks  <3=> 4 clks
  371 00004800         ;//                   <4=> 6 clk   <5=> 8 clks  <6=> 10 
                       clks <7=> 14 clks
  372 00004800         ;//       <o6.11..12> Tcos: Chip Select Set-up nOE
  373 00004800         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  374 00004800         ;//       <o6.13..14> Tacs: Address Set-up before nGCSn
  375 00004800         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  376 00004800         ;//     </h>
  377 00004800         ;//     <h> SDRAM
  378 00004800         ;//       <o6.0..1>   SCAN: Columnn Address Number
  379 00004800         ;//                   <0=> 8-bit   <1=> 9-bit   <2=> 10-
                       bit  <3=> Rsrvd
  380 00004800         ;//       <o6.2..3>   Trcd: RAS to CAS Delay
  381 00004800         ;//                   <0=> 2 clks  <1=> 3 clks  <2=> 4 c
                       lks  <3=> Rsrvd
  382 00004800         ;//       <o10.4>     SCKEEN: SCLK Selection (Bank 6/7)
  383 00004800         ;//                   <0=> Normal
  384 00004800         ;//                   <1=> Reduced Power   
  385 00004800         ;//       <o10.5>     SCLKEN: SDRAM power down mode (Ban
                       k 6/7)
  386 00004800         ;//                   <0=> DISABLE
  387 00004800         ;//                   <1=> ENABLE 
  388 00004800         ;//       <o10.7>     BURST_EN: ARM core burst operation
                        (Bank 6/7)
  389 00004800         ;//                   <0=> DISABLE
  390 00004800         ;//                   <1=> ENABLE 
  391 00004800         ;//       <o11.0..2>  BL: Burst Length
  392 00004800         ;//                   <0=> 1
  393 00004800         ;//       <o11.3>     BT: Burst Type
  394 00004800         ;//                   <0=> Sequential
  395 00004800         ;//       <o11.4..6>  CL: CAS Latency
  396 00004800         ;//                   <0=> 1 clk   <1=> 2 clks  <2=> 3 c
                       lks
  397 00004800         ;//       <o11.7..8>  TM: Test Mode
  398 00004800         ;//                   <0=> Mode Register Set
  399 00004800         ;//       <o11.9>     WBL: Write Burst Length
  400 00004800         ;//                   <0=> 0
  401 00004800         ;//     </h>
  402 00004800         ;//   </h>
  403 00004800         ;//
  404 00004800         ;//   <h> Bank 7
  405 00004800         ;//     <o10.0..2>  BK76MAP: Bank 6/7 Memory Map
  406 00004800         ;//                 <0=> 32M  <1=> 64M <2=> 128M <4=> 2M
                          <5=> 4M   <6=> 8M   <7=> 16M
  407 00004800         ;//     <o8.28..29> DW: Data Bus Width
  408 00004800         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  409 00004800         ;//     <o8.30>     WS: WAIT Status
  410 00004800         ;//                 <0=> WAIT Disable
  411 00004800         ;//                 <1=> WAIT Enable
  412 00004800         ;//     <o8.31>     ST: SRAM Type



ARM Macro Assembler    Page 12 


  413 00004800         ;//                 <0=> Not using UB/LB
  414 00004800         ;//                 <1=> Using UB/LB
  415 00004800         ;//     <o7.15..16> MT: Memory Type
  416 00004800         ;//                 <0=> ROM or SRAM
  417 00004800         ;//                 <3=> SDRAM
  418 00004800         ;//     <h> ROM or SRAM
  419 00004800         ;//       <o7.0..1>   PMC: Page Mode Configuration
  420 00004800         ;//                   <0=> 1 Data  <1=> 4 Data  <2=> 8 D
                       ata  <3=> 16 Data
  421 00004800         ;//       <o7.2..3>   Tpac: Page Mode Access Cycle
  422 00004800         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  423 00004800         ;//       <o7.4..5>   Tcah: Address Holding Time after n
                       GCSn
  424 00004800         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  425 00004800         ;//       <o7.6..7>   Toch: Chip Select Hold on nOE
  426 00004800         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  427 00004800         ;//       <o7.8..10>  Tacc: Access Cycle
  428 00004800         ;//                   <0=> 1 clk   <1=> 2 clks  <2=> 3 c
                       lks  <3=> 4 clks
  429 00004800         ;//                   <4=> 6 clk   <5=> 8 clks  <6=> 10 
                       clks <7=> 14 clks
  430 00004800         ;//       <o7.11..12> Tcos: Chip Select Set-up nOE
  431 00004800         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  432 00004800         ;//       <o7.13..14> Tacs: Address Set-up before nGCSn
  433 00004800         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  434 00004800         ;//     </h>
  435 00004800         ;//     <h> SDRAM
  436 00004800         ;//       <o7.0..1>   SCAN: Columnn Address Number
  437 00004800         ;//                   <0=> 8-bit   <1=> 9-bit   <2=> 10-
                       bit  <3=> Rsrvd
  438 00004800         ;//       <o7.2..3>   Trcd: RAS to CAS Delay
  439 00004800         ;//                   <0=> 2 clks  <1=> 3 clks  <2=> 4 c
                       lks  <3=> Rsrvd
  440 00004800         ;//       <o10.4>     SCLKEN: SCLK Selection (Bank 6/7)
  441 00004800         ;//                   <0=> Normal
  442 00004800         ;//                   <1=> Reduced Power 
  443 00004800         ;//       <o10.5>     SCLKEN: SDRAM power down mode (Ban
                       k 6/7)
  444 00004800         ;//                   <0=> DISABLE
  445 00004800         ;//                   <1=> ENABLE 
  446 00004800         ;//       <o10.7>     BURST_EN: ARM core burst operation
                        (Bank 6/7)
  447 00004800         ;//                   <0=> DISABLE
  448 00004800         ;//                   <1=> ENABLE 
  449 00004800         ;//       <o12.0..2>  BL: Burst Length
  450 00004800         ;//                   <0=> 1
  451 00004800         ;//       <o12.3>     BT: Burst Type
  452 00004800         ;//                   <0=> Sequential
  453 00004800         ;//       <o12.4..6>  CL: CAS Latency
  454 00004800         ;//                   <0=> 1 clk   <1=> 2 clks  <2=> 3 c
                       lks
  455 00004800         ;//       <o12.7..8>  TM: Test Mode
  456 00004800         ;//                   <0=> Mode Register Set
  457 00004800         ;//       <o12.9>     WBL: Write Burst Length



ARM Macro Assembler    Page 13 


  458 00004800         ;//                   <0=> 0
  459 00004800         ;//     </h>
  460 00004800         ;//   </h>
  461 00004800         ;//
  462 00004800         ;//   <h> Refresh
  463 00004800         ;//     <o9.23>     REFEN: SDRAM Refresh
  464 00004800         ;//                 <0=> Disable <1=> Enable
  465 00004800         ;//     <o9.22>     TREFMD: SDRAM Refresh Mode
  466 00004800         ;//                 <0=> CBR/Auto Refresh
  467 00004800         ;//                 <1=> Self Refresh
  468 00004800         ;//     <o9.20..21> Trp: SDRAM RAS Pre-charge Time
  469 00004800         ;//                 <0=> 2 clks 
  470 00004800         ;//                 <1=> 3 clks 
  471 00004800         ;//                 <2=> 4 clks 
  472 00004800         ;//                 <3=> Rsrvd 
  473 00004800         ;//     <o9.18..19> Tsrc: SDRAM Semi Row cycle time
  474 00004800         ;//                <i> SDRAM Row cycle time: Trc=Tsrc+Tr
                       p
  475 00004800         ;//                 <0=> 4 clks  <1=> 5 clks  <2=> 6 clk
                       s  <3=> 7 clks
  476 00004800         ;//     <o9.0..10>  Refresh Counter <0x0-0x07FF>
  477 00004800         ;//                 <i> Refresh Period = (2^11 - Refresh
                        Count + 1) / HCLK
  478 00004800         ;//   </h>
  479 00004800 00000700 
                       BANKCON0_Val
                               EQU              0x00000700
  480 00004800 00000700 
                       BANKCON1_Val
                               EQU              0x00000700
  481 00004800 00000700 
                       BANKCON2_Val
                               EQU              0x00000700
  482 00004800 00000700 
                       BANKCON3_Val
                               EQU              0x00000700
  483 00004800 00000700 
                       BANKCON4_Val
                               EQU              0x00000700
  484 00004800 00000700 
                       BANKCON5_Val
                               EQU              0x00000700
  485 00004800 00018005 
                       BANKCON6_Val
                               EQU              0x00018005
  486 00004800 00018005 
                       BANKCON7_Val
                               EQU              0x00018005
  487 00004800 22119120 
                       BWSCON_Val
                               EQU              0X22119120  ;0x22111110  
  488 00004800 008E0459 
                       REFRESH_Val
                               EQU              0x008e0459
  489 00004800 00000032 
                       BANKSIZE_Val
                               EQU              0x00000032  ;0x000000b2
  490 00004800 00000030 
                       MRSRB6_Val



ARM Macro Assembler    Page 14 


                               EQU              0x00000030
  491 00004800 00000030 
                       MRSRB7_Val
                               EQU              0x00000030
  492 00004800         
  493 00004800         ;// </e> End of MC
  494 00004800         
  495 00004800         
  496 00004800         
  497 00004800         ; I/O Ports definitions
  498 00004800 56000000 
                       PIO_BASE
                               EQU              0x56000000  ; PIO Base Address
  499 00004800 00000000 
                       PCONA_OFS
                               EQU              0x00        ; PCONA Offset
  500 00004800 00000010 
                       PCONB_OFS
                               EQU              0x10        ; PCONB Offset
  501 00004800 00000020 
                       PCONC_OFS
                               EQU              0x20        ; PCONC Offset
  502 00004800 00000030 
                       PCOND_OFS
                               EQU              0x30        ; PCOND Offset
  503 00004800 00000040 
                       PCONE_OFS
                               EQU              0x40        ; PCONE Offset
  504 00004800 00000050 
                       PCONF_OFS
                               EQU              0x50        ; PCONF Offset
  505 00004800 00000060 
                       PCONG_OFS
                               EQU              0x60        ; PCONG Offset
  506 00004800 00000070 
                       PCONH_OFS
                               EQU              0x70        ; PCONH Offset
  507 00004800 000000D0 
                       PCONJ_OFS
                               EQU              0xD0        ; PCONJ Offset
  508 00004800 00000018 
                       PUPB_OFS
                               EQU              0x18        ; PUPB Offset
  509 00004800 00000028 
                       PUPC_OFS
                               EQU              0x28        ; PUPC Offset
  510 00004800 00000038 
                       PUPD_OFS
                               EQU              0x38        ; PUPD Offset
  511 00004800 00000048 
                       PUPE_OFS
                               EQU              0x48        ; PUPE Offset
  512 00004800 00000058 
                       PUPF_OFS
                               EQU              0x58        ; PUPF Offset
  513 00004800 00000068 
                       PUPG_OFS
                               EQU              0x68        ; PUPG Offset
  514 00004800 00000078 



ARM Macro Assembler    Page 15 


                       PUPH_OFS
                               EQU              0x78        ; PUPH Offset
  515 00004800 000000D8 
                       PUPJ_OFS
                               EQU              0xD8        ; PUPJ Offset
  516 00004800         
  517 00004800         
  518 00004800         ;// <e> I/O Configuration
  519 00004800 00000001 
                       PIO_SETUP
                               EQU              1
  520 00004800         
  521 00004800         ;//   <e> Port A
  522 00004800         ;//     <o1.0>      PA0  <0=> Output   <1=> ADDR0
  523 00004800         ;//     <o1.1>      PA1  <0=> Output   <1=> ADDR16
  524 00004800         ;//     <o1.2>      PA2  <0=> Output   <1=> ADDR17
  525 00004800         ;//     <o1.3>      PA3  <0=> Output   <1=> ADDR18
  526 00004800         ;//     <o1.4>      PA4  <0=> Output   <1=> ADDR19
  527 00004800         ;//     <o1.5>      PA5  <0=> Output   <1=> ADDR20
  528 00004800         ;//     <o1.6>      PA6  <0=> Output   <1=> ADDR21
  529 00004800         ;//     <o1.7>      PA7  <0=> Output   <1=> ADDR22
  530 00004800         ;//     <o1.8>      PA8  <0=> Output   <1=> ADDR23
  531 00004800         ;//     <o1.9>      PA9  <0=> Output   <1=> ADDR24
  532 00004800         ;//     <o1.10>      PA0  <0=> Output   <1=> ADDR25
  533 00004800         ;//     <o1.11>      PA1  <0=> Output   <1=> ADDR26
  534 00004800         ;//     <o1.12>      PA2  <0=> Output   <1=> nGCS[1]
  535 00004800         ;//     <o1.13>      PA3  <0=> Output   <1=> nGCS[2]
  536 00004800         ;//     <o1.14>      PA4  <0=> Output   <1=> nGCS[3]
  537 00004800         ;//     <o1.15>      PA5  <0=> Output   <1=> nGCS[4]
  538 00004800         ;//     <o1.16>      PA6  <0=> Output   <1=> nGCS[5]
  539 00004800         ;//     <o1.17>      PA7  <0=> Output   <1=> CLE
  540 00004800         ;//     <o1.18>      PA8  <0=> Output   <1=> ALE
  541 00004800         ;//     <o1.19>      PA9  <0=> Output   <1=> nFWE
  542 00004800         ;//     <o1.20>      PA0  <0=> Output   <1=> nFRE
  543 00004800         ;//     <o1.21>      PA1  <0=> Output   <1=> nRSTOUT
  544 00004800         ;//     <o1.22>      PA2  <0=> Output   <1=> nFCE
  545 00004800         ;//   </e>
  546 00004800 00000000 
                       PIOA_SETUP
                               EQU              0
  547 00004800 000003FF 
                       PCONA_Val
                               EQU              0x000003FF
  548 00004800         
  549 00004800         ;//   <e> Port B
  550 00004800         ;//     <o1.0..1>        PB0  <0=> Input   <1=> Output  
                       <2=> TOUT0    <3=> Reserved 
  551 00004800         ;//     <o1.2..3>        PB1  <0=> Input   <1=> Output  
                       <2=> TOUT1    <3=> Reserved 
  552 00004800         ;//     <o1.4..5>        PB2  <0=> Input   <1=> Output  
                       <2=> TOUT2    <3=> Reserved 
  553 00004800         ;//     <o1.6..7>        PB3  <0=> Input   <1=> Output  
                       <2=> TOUT3    <3=> Reserved 
  554 00004800         ;//     <o1.8..9>        PB4  <0=> Input   <1=> Output  
                       <2=> TCLK[0]  <3=> Reserved 
  555 00004800         ;//     <o1.10..11>      PB5  <0=> Input   <1=> Output  
                       <2=> nXBACK   <3=> Reserved 
  556 00004800         ;//     <o1.12..13>      PB6  <0=> Input   <1=> Output  
                       <2=> nXBREQ   <3=> Reserved 



ARM Macro Assembler    Page 16 


  557 00004800         ;//     <o1.14..15>      PB7  <0=> Input   <1=> Output  
                       <2=> nXDACK1  <3=> Reserved 
  558 00004800         ;//     <o1.16..17>      PB8  <0=> Input   <1=> Output  
                       <2=> nXDREQ1  <3=> Reserved 
  559 00004800         ;//     <o1.18..19>      PB9  <0=> Input   <1=> Output  
                       <2=> nXDACK0  <3=> Reserved 
  560 00004800         ;//     <o1.20..21>      PB10 <0=> Input   <1=> Output  
                       <2=> nXDREQ0  <3=> Reserved 
  561 00004800         ;//     <h> Pull-up Resistors                           
                                    
  562 00004800         ;//       <o2.0>    PB0 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  563 00004800         ;//       <o2.1>    PB1 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  564 00004800         ;//       <o2.2>    PB2 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  565 00004800         ;//       <o2.3>    PB3 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  566 00004800         ;//       <o2.4>    PB4 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  567 00004800         ;//       <o2.5>    PB5 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  568 00004800         ;//       <o2.6>    PB6 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  569 00004800         ;//       <o2.7>    PB7 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  570 00004800         ;//       <o2.8>    PB8 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  571 00004800         ;//       <o2.9>    PB9 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  572 00004800         ;//       <o2.10>   PB10 Pull-up       <0=> Enabled  <1=
                       > Disabled   
  573 00004800         ;//     </h>                                            
                                    
  574 00004800         ;//   </e>
  575 00004800 00000000 
                       PIOB_SETUP
                               EQU              0
  576 00004800 000007FF 
                       PCONB_Val
                               EQU              0x000007FF
  577 00004800 00000000 
                       PUPB_Val
                               EQU              0x00000000
  578 00004800         
  579 00004800         ;//   <e> Port C
  580 00004800         ;//     <o1.0..1>          PC0  <0=> Input    <1=> Outpu
                       t  <2=> LEND          <3=> Reserved 
  581 00004800         ;//     <o1.2..3>          PC1  <0=> Input    <1=> Outpu
                       t  <2=> VCLK          <3=> Reserved 
  582 00004800         ;//     <o1.4..5>          PC2  <0=> Input    <1=> Outpu
                       t  <2=> VLINE         <3=> Reserved 
  583 00004800         ;//     <o1.6..7>          PC3  <0=> Input    <1=> Outpu
                       t  <2=> VFRAME        <3=> Reserved 
  584 00004800         ;//     <o1.8..9>          PC4  <0=> Input    <1=> Outpu
                       t  <2=> VM            <3=> Reserved 
  585 00004800         ;//     <o1.10..11>        PC5  <0=> Input    <1=> Outpu
                       t  <2=> LCDVF2     <3=> Reserved 
  586 00004800         ;//     <o1.12..13>        PC6  <0=> Input    <1=> Outpu



ARM Macro Assembler    Page 17 


                       t  <2=> LCDVF1    <3=> Reserved 
  587 00004800         ;//     <o1.14..15>        PC7  <0=> Input    <1=> Outpu
                       t  <2=> LCDVF0   <3=> Reserved 
  588 00004800         ;//     <o1.16..17>        PC8  <0=> Input    <1=> Outpu
                       t  <2=> VD[0]         <3=> Reserved 
  589 00004800         ;//     <o1.18..19>        PC9  <0=> Input    <1=> Outpu
                       t  <2=> VD[1]         <3=> Reserved 
  590 00004800         ;//     <o1.20..21>        PC10 <0=> Input    <1=> Outpu
                       t  <2=> VD[2]         <3=> Reserved 
  591 00004800         ;//     <o1.22..23>        PC11  <0=> Input   <1=> Outpu
                       t  <2=> VD[3]         <3=> Reserved 
  592 00004800         ;//     <o1.24..25>        PC12  <0=> Input   <1=> Outpu
                       t  <2=> VD[4]         <3=> Reserved 
  593 00004800         ;//     <o1.26..27>        PC13  <0=> Input   <1=> Outpu
                       t  <2=> VD[5]         <3=> Reserved 
  594 00004800         ;//     <o1.28..29>        PC14  <0=> Input   <1=> Outpu
                       t  <2=> VD[6]         <3=> Reserved 
  595 00004800         ;//     <o1.30..31>        PC15  <0=> Input   <1=> Outpu
                       t  <2=> VD[7]         <3=> Reserved 
  596 00004800         ;//     <h> Pull-up Resistors                           
                                    
  597 00004800         ;//       <o2.0>     PC0 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  598 00004800         ;//       <o2.1>     PC1 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  599 00004800         ;//       <o2.2>     PC2 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  600 00004800         ;//       <o2.3>     PC3 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  601 00004800         ;//       <o2.4>     PC4 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  602 00004800         ;//       <o2.5>     PC5 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  603 00004800         ;//       <o2.6>     PC6 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  604 00004800         ;//       <o2.7>     PC7 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  605 00004800         ;//       <o2.8>     PC8 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  606 00004800         ;//       <o2.9>     PC9 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  607 00004800         ;//       <o2.10>    PC10 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  608 00004800         ;//       <o2.11>    PC11 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  609 00004800         ;//       <o2.12>    PC12 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  610 00004800         ;//       <o2.13>    PC13 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  611 00004800         ;//       <o2.14>    PC14 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  612 00004800         ;//       <o2.15>    PC15 Pull-up        <0=> Enabled  <
                       1=> Disabled  
  613 00004800         ;//     </h>                                            
                                    
  614 00004800         ;//   </e>
  615 00004800 00000000 
                       PIOC_SETUP
                               EQU              0



ARM Macro Assembler    Page 18 


  616 00004800 AAAAAAAA 
                       PCONC_Val
                               EQU              0xAAAAAAAA
  617 00004800 00000000 
                       PUPC_Val
                               EQU              0x00000000
  618 00004800         
  619 00004800         ;//   <e> Port D
  620 00004800         ;//     <o1.0..1>          PD0  <0=> Input    <1=> Outpu
                       t  <2=> VD[8]         <3=> Reserved 
  621 00004800         ;//     <o1.2..3>          PD1  <0=> Input    <1=> Outpu
                       t  <2=> VD[9]         <3=> Reserved 
  622 00004800         ;//     <o1.4..5>          PD2  <0=> Input    <1=> Outpu
                       t  <2=> VD[10]         <3=> Reserved 
  623 00004800         ;//     <o1.6..7>          PD3  <0=> Input    <1=> Outpu
                       t  <2=> VD[11]         <3=> Reserved 
  624 00004800         ;//     <o1.8..9>          PD4  <0=> Input    <1=> Outpu
                       t  <2=> VD[12]         <3=> Reserved 
  625 00004800         ;//     <o1.10..11>        PD5  <0=> Input    <1=> Outpu
                       t  <2=> VD[13]         <3=> Reserved 
  626 00004800         ;//     <o1.12..13>        PD6  <0=> Input    <1=> Outpu
                       t  <2=> VD[14]         <3=> Reserved 
  627 00004800         ;//     <o1.14..15>        PD7  <0=> Input    <1=> Outpu
                       t  <2=> VD[15]         <3=> Reserved 
  628 00004800         ;//     <o1.16..17>        PD8  <0=> Input    <1=> Outpu
                       t  <2=> VD[16]         <3=> Reserved  
  629 00004800         ;//     <o1.18..19>        PD9  <0=> Input    <1=> Outpu
                       t  <2=> VD[17]         <3=> Reserved 
  630 00004800         ;//     <o1.20..21>        PD10 <0=> Input    <1=> Outpu
                       t  <2=> VD[18]         <3=> Reserved 
  631 00004800         ;//     <o1.22..23>        PD11  <0=> Input   <1=> Outpu
                       t  <2=> VD[19]         <3=> Reserved 
  632 00004800         ;//     <o1.24..25>        PD12  <0=> Input   <1=> Outpu
                       t  <2=> VD[20]         <3=> Reserved 
  633 00004800         ;//     <o1.26..27>        PD13  <0=> Input   <1=> Outpu
                       t  <2=> VD[21]         <3=> Reserved 
  634 00004800         ;//     <o1.28..29>        PD14  <0=> Input   <1=> Outpu
                       t  <2=> VD[22]          <3=> nSS1
  635 00004800         ;//     <o1.30..31>        PD15  <0=> Input   <1=> Outpu
                       t  <2=> VD[23]          <3=> nSS0 
  636 00004800         ;//     <h> Pull-up Resistors                           
                                    
  637 00004800         ;//       <o2.0>     PD0 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  638 00004800         ;//       <o2.1>     PD1 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  639 00004800         ;//       <o2.2>     PD2 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  640 00004800         ;//       <o2.3>     PD3 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  641 00004800         ;//       <o2.4>     PD4 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  642 00004800         ;//       <o2.5>     PD5 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  643 00004800         ;//       <o2.6>     PD6 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  644 00004800         ;//       <o2.7>     PD7 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  645 00004800         ;//       <o2.8>     PD8 Pull-up         <0=> Enabled  <



ARM Macro Assembler    Page 19 


                       1=> Disabled   
  646 00004800         ;//       <o2.9>     PD9 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  647 00004800         ;//       <o2.10>    PD10 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  648 00004800         ;//       <o2.11>    PD11 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  649 00004800         ;//       <o2.12>    PD12 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  650 00004800         ;//       <o2.13>    PD13 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  651 00004800         ;//       <o2.14>    PD14 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  652 00004800         ;//       <o2.15>    PD15 Pull-up        <0=> Enabled  <
                       1=> Disabled  
  653 00004800         ;//     </h>         
  654 00004800         ;//   </e>
  655 00004800 00000000 
                       PIOD_SETUP
                               EQU              0
  656 00004800 00000000 
                       PCOND_Val
                               EQU              0x00000000
  657 00004800 00000000 
                       PUPD_Val
                               EQU              0x00000000
  658 00004800         
  659 00004800         ;//   <e> Port E
  660 00004800         ;//     <o1.0..1>          PE0  <0=> Input    <1=> Outpu
                       t  <2=> I2SLRCK       <3=> Reserved 
  661 00004800         ;//     <o1.2..3>          PE1  <0=> Input    <1=> Outpu
                       t  <2=> I2SSCLK       <3=> Reserved  
  662 00004800         ;//     <o1.4..5>          PE2  <0=> Input    <1=> Outpu
                       t  <2=> CDCLK         <3=> Reserved 
  663 00004800         ;//     <o1.6..7>          PE3  <0=> Input    <1=> Outpu
                       t  <2=> I2SDI         <3=> nSS0 
  664 00004800         ;//     <o1.8..9>          PE4  <0=> Input    <1=> Outpu
                       t  <2=> I2SDO         <3=> I2SSDI 
  665 00004800         ;//     <o1.10..11>        PE5  <0=> Input    <1=> Outpu
                       t  <2=> SDCLK         <3=> Reserved 
  666 00004800         ;//     <o1.12..13>        PE6  <0=> Input    <1=> Outpu
                       t  <2=> SDCMD         <3=> Reserved 
  667 00004800         ;//     <o1.14..15>        PE7  <0=> Input    <1=> Outpu
                       t  <2=> SDDAT0        <3=> Reserved 
  668 00004800         ;//     <o1.16..17>        PE8  <0=> Input    <1=> Outpu
                       t  <2=> SDDAT1        <3=> Reserved
  669 00004800         ;//     <o1.18..19>        PE9  <0=> Input    <1=> Outpu
                       t  <2=> SDDAT2        <3=> Reserved
  670 00004800         ;//     <o1.20..21>        PE10 <0=> Input    <1=> Outpu
                       t  <2=> SDDAT3        <3=> Reserved
  671 00004800         ;//     <o1.22..23>        PE11  <0=> Input   <1=> Outpu
                       t  <2=> SPIMISO0      <3=> Reserved 
  672 00004800         ;//     <o1.24..25>        PE12  <0=> Input   <1=> Outpu
                       t  <2=> SPIMOSI0      <3=> Reserved 
  673 00004800         ;//     <o1.26..27>        PE13  <0=> Input   <1=> Outpu
                       t  <2=> SPICLK0       <3=> Reserved 
  674 00004800         ;//     <o1.28..29>        PE14  <0=> Input   <1=> Outpu
                       t  <2=> IICSCL        <3=> Reserved
  675 00004800         ;//     <o1.30..31>        PE15  <0=> Input   <1=> Outpu



ARM Macro Assembler    Page 20 


                       t  <2=> IICSDA        <3=> Reserved
  676 00004800         ;//     <h> Pull-up Resistors                           
                                                  
  677 00004800         ;//       <o2.0>     PE0 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  678 00004800         ;//       <o2.1>     PE1 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  679 00004800         ;//       <o2.2>     PE2 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  680 00004800         ;//       <o2.3>     PE3 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  681 00004800         ;//       <o2.4>     PE4 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  682 00004800         ;//       <o2.5>     PE5 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  683 00004800         ;//       <o2.6>     PE6 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  684 00004800         ;//       <o2.7>     PE7 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  685 00004800         ;//       <o2.8>     PE8 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  686 00004800         ;//       <o2.9>     PE9 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  687 00004800         ;//       <o2.10>    PE10 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  688 00004800         ;//       <o2.11>    PE11 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  689 00004800         ;//       <o2.12>    PE12 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  690 00004800         ;//       <o2.13>    PE13 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  691 00004800         ;//       <o2.14>    PE14 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  692 00004800         ;//       <o2.15>    PE15 Pull-up        <0=> Enabled  <
                       1=> Disabled  
  693 00004800         ;//     </h>         
  694 00004800         ;//   </e>
  695 00004800 00000000 
                       PIOE_SETUP
                               EQU              0
  696 00004800 00000000 
                       PCONE_Val
                               EQU              0x00000000
  697 00004800 00000000 
                       PUPE_Val
                               EQU              0x00000000
  698 00004800         
  699 00004800         ;//   <e> Port F
  700 00004800         ;//     <o1.0..1>        PF0  <0=> Input   <1=> Output  
                       <2=> EINT[0]  <3=> Reserved 
  701 00004800         ;//     <o1.2..3>        PF1  <0=> Input   <1=> Output  
                       <2=> EINT[1]  <3=> Reserved 
  702 00004800         ;//     <o1.4..5>        PF2  <0=> Input   <1=> Output  
                       <2=> EINT[2]  <3=> Reserved 
  703 00004800         ;//     <o1.6..7>        PF3  <0=> Input   <1=> Output  
                       <2=> EINT[3]  <3=> Reserved 
  704 00004800         ;//     <o1.8..9>        PF4  <0=> Input   <1=> Output  
                       <2=> EINT[4]  <3=> Reserved 
  705 00004800         ;//     <o1.10..11>      PF5  <0=> Input   <1=> Output  



ARM Macro Assembler    Page 21 


                       <2=> EINT[5]  <3=> Reserved 
  706 00004800         ;//     <o1.12..13>      PF6  <0=> Input   <1=> Output  
                       <2=> EINT[6]  <3=> Reserved 
  707 00004800         ;//     <o1.14..15>      PF7  <0=> Input   <1=> Output  
                       <2=> EINT[7]  <3=> Reserved 
  708 00004800         ;//     <h> Pull-up Resistors                           
                                    
  709 00004800         ;//       <o2.0>    PF0 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  710 00004800         ;//       <o2.1>    PF1 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  711 00004800         ;//       <o2.2>    PF2 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  712 00004800         ;//       <o2.3>    PF3 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  713 00004800         ;//       <o2.4>    PF4 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  714 00004800         ;//       <o2.5>    PF5 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  715 00004800         ;//       <o2.6>    PF6 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  716 00004800         ;//       <o2.7>    PF7 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  717 00004800         ;//     </h> 
  718 00004800         ;//   </e>
  719 00004800 00000001 
                       PIOF_SETUP
                               EQU              1
  720 00004800 000055AA 
                       PCONF_Val
                               EQU              0x000055aa
  721 00004800 000000FF 
                       PUPF_Val
                               EQU              0x000000ff
  722 00004800         
  723 00004800         ;//   <e> Port G
  724 00004800         ;//     <o1.0..1>          PG0  <0=> Input    <1=> Outpu
                       t  <2=> EINT[8]   <3=> Reserved 
  725 00004800         ;//     <o1.2..3>          PG1  <0=> Input    <1=> Outpu
                       t  <2=> EINT[9]   <3=> Reserved 
  726 00004800         ;//     <o1.4..5>          PG2  <0=> Input    <1=> Outpu
                       t  <2=> EINT[10]   <3=> nSS0 
  727 00004800         ;//     <o1.6..7>          PG3  <0=> Input    <1=> Outpu
                       t  <2=> EINT[11]   <3=> nSS1 
  728 00004800         ;//     <o1.8..9>          PG4  <0=> Input    <1=> Outpu
                       t  <2=> EINT[12]   <3=> LCD_PWRDN 
  729 00004800         ;//     <o1.10..11>        PG5  <0=> Input    <1=> Outpu
                       t  <2=> EINT[13]   <3=> SPIMISO1 
  730 00004800         ;//     <o1.12..13>        PG6  <0=> Input    <1=> Outpu
                       t  <2=> EINT[14]   <3=> SPIMOSI1
  731 00004800         ;//     <o1.14..15>        PG7  <0=> Input    <1=> Outpu
                       t  <2=> EINT[15]   <3=> SPICLK1 
  732 00004800         ;//     <o1.16..17>        PG8  <0=> Input    <1=> Outpu
                       t  <2=> EINT[16]   <3=> Reserved 
  733 00004800         ;//     <o1.18..19>        PG9  <0=> Input    <1=> Outpu
                       t  <2=> EINT[17]   <3=> Reserved 
  734 00004800         ;//     <o1.20..21>        PG10 <0=> Input    <1=> Outpu
                       t  <2=> EINT[18]   <3=> Reserved 
  735 00004800         ;//     <o1.22..23>        PG11  <0=> Input   <1=> Outpu



ARM Macro Assembler    Page 22 


                       t  <2=> EINT[19]   <3=> TCLK1
  736 00004800         ;//     <o1.24..25>        PG12  <0=> Input   <1=> Outpu
                       t  <2=> EINT[20]   <3=> XMON
  737 00004800         ;//     <o1.26..27>        PG13  <0=> Input   <1=> Outpu
                       t  <2=> EINT[21]   <3=> nXPON 
  738 00004800         ;//     <o1.28..29>        PG14  <0=> Input   <1=> Outpu
                       t  <2=> EINT[22]   <3=> YMON
  739 00004800         ;//     <o1.30..31>        PG15  <0=> Input   <1=> Outpu
                       t  <2=> EINT[23]   <3=> nYPON
  740 00004800         ;//     <h> Pull-up Resistors                           
                                    
  741 00004800         ;//       <o2.0>     PG0 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  742 00004800         ;//       <o2.1>     PG1 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  743 00004800         ;//       <o2.2>     PG2 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  744 00004800         ;//       <o2.3>     PG3 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  745 00004800         ;//       <o2.4>     PG4 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  746 00004800         ;//       <o2.5>     PG5 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  747 00004800         ;//       <o2.6>     PG6 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  748 00004800         ;//       <o2.7>     PG7 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  749 00004800         ;//       <o2.8>     PG8 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  750 00004800         ;//       <o2.9>     PG9 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  751 00004800         ;//       <o2.10>    PG10 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  752 00004800         ;//       <o2.11>    PG11 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  753 00004800         ;//       <o2.12>    PG12 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  754 00004800         ;//       <o2.13>    PG13 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  755 00004800         ;//       <o2.14>    PG14 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  756 00004800         ;//       <o2.15>    PG15 Pull-up        <0=> Enabled  <
                       1=> Disabled  
  757 00004800         ;//     </h>                                            
                               
  758 00004800         ;//   </e>
  759 00004800 00000000 
                       PIOG_SETUP
                               EQU              0
  760 00004800 00000000 
                       PCONG_Val
                               EQU              0x00000000
  761 00004800 00000000 
                       PUPG_Val
                               EQU              0x00000000
  762 00004800         
  763 00004800         ;//   <e> Port H
  764 00004800         ;//     <o1.0..1>        PH0  <0=> Input   <1=> Output  
                       <2=> nCTS0    <3=> Reserved 



ARM Macro Assembler    Page 23 


  765 00004800         ;//     <o1.2..3>        PH1  <0=> Input   <1=> Output  
                       <2=> nRTS0    <3=> Reserved 
  766 00004800         ;//     <o1.4..5>        PH2  <0=> Input   <1=> Output  
                       <2=> TXD[0]    <3=> Reserved 
  767 00004800         ;//     <o1.6..7>        PH3  <0=> Input   <1=> Output  
                       <2=> RXD[0]    <3=> Reserved 
  768 00004800         ;//     <o1.8..9>        PH4  <0=> Input   <1=> Output  
                       <2=> TXD[1]  <3=> Reserved 
  769 00004800         ;//     <o1.10..11>      PH5  <0=> Input   <1=> Output  
                       <2=> RXD[1]   <3=> Reserved 
  770 00004800         ;//     <o1.12..13>      PH6  <0=> Input   <1=> Output  
                       <2=> TXD[2]   <3=> nRTS1
  771 00004800         ;//     <o1.14..15>      PH7  <0=> Input   <1=> Output  
                       <2=> RXD[2]  <3=> nCTS1 
  772 00004800         ;//     <o1.16..17>      PH8  <0=> Input   <1=> Output  
                       <2=> UCLK    <3=> Reserved 
  773 00004800         ;//     <o1.18..19>      PH9  <0=> Input   <1=> Output  
                       <2=> CLKOUT0  <3=> Reserved 
  774 00004800         ;//     <o1.20..21>      PH10 <0=> Input   <1=> Output  
                       <2=> CLKOUT1  <3=> Reserved 
  775 00004800         ;//     <h> Pull-up Resistors                           
                                    
  776 00004800         ;//       <o2.0>    PH0 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  777 00004800         ;//       <o2.1>    PH1 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  778 00004800         ;//       <o2.2>    PH2 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  779 00004800         ;//       <o2.3>    PH3 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  780 00004800         ;//       <o2.4>    PH4 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  781 00004800         ;//       <o2.5>    PH5 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  782 00004800         ;//       <o2.6>    PH6 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  783 00004800         ;//       <o2.7>    PH7 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  784 00004800         ;//       <o2.8>    PH8 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  785 00004800         ;//       <o2.9>    PH9 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  786 00004800         ;//       <o2.10>   PH10 Pull-up       <0=> Enabled  <1=
                       > Disabled   
  787 00004800         ;//     </h>                                            
                                    
  788 00004800         ;//   </e>
  789 00004800 00000000 
                       PIOH_SETUP
                               EQU              0
  790 00004800 000007FF 
                       PCONH_Val
                               EQU              0x000007FF
  791 00004800 00000000 
                       PUPH_Val
                               EQU              0x00000000
  792 00004800         
  793 00004800         ;// </e>
  794 00004800         



ARM Macro Assembler    Page 24 


  795 00004800         
  796 00004800         
  797 00004800         
  798 00004800                 PRESERVE8
  799 00004800         
  800 00004800         
  801 00004800         ; Area Definition and Entry Point
  802 00004800         ;  Startup Code must be linked first at Address at which
                        it expects to run.
  803 00004800         
  804 00004800                 AREA             RESET, CODE, READONLY
  805 00000000                 ARM
  806 00000000         
  807 00000000         
  808 00000000         ; Exception Vectors
  809 00000000         ;  Mapped to Address 0.
  810 00000000         ;  Absolute addressing mode must be used.
  811 00000000         ;  Dummy Handlers are implemented as infinite loops whic
                       h can be modified.
  812 00000000         
  813 00000000 E59FF03C 
                       Vectors LDR              PC, Reset_Addr
  814 00000004 E59FF03C        LDR              PC, Undef_Addr
  815 00000008 E59FF03C        LDR              PC, SWI_Addr
  816 0000000C E59FF03C        LDR              PC, PAbt_Addr
  817 00000010 E59FF03C        LDR              PC, DAbt_Addr
  818 00000014 E1A00000        NOP                          ; Reserved Vector 
  819 00000018 E59FF03C        LDR              PC, IRQ_Addr
  820 0000001C E59FF03C        LDR              PC, FIQ_Addr
  821 00000020         
  822 00000020         
  823 00000020                 IF               IntVT_SETUP <> 0
  824 00000020         
  825 00000020         ;Interrupt Vector Table Address                
  826 00000020 33FFFF20 
                       HandleEINT0
                               EQU              IntVTAddress
  827 00000020 33FFFF24 
                       HandleEINT1
                               EQU              IntVTAddress +4
  828 00000020 33FFFF28 
                       HandleEINT2
                               EQU              IntVTAddress +4*2
  829 00000020 33FFFF2C 
                       HandleEINT3
                               EQU              IntVTAddress +4*3
  830 00000020 33FFFF30 
                       HandleEINT4_7
                               EQU              IntVTAddress +4*4
  831 00000020 33FFFF34 
                       HandleEINT8_23
                               EQU              IntVTAddress +4*5
  832 00000020 33FFFF38 
                       HandleReserved
                               EQU              IntVTAddress +4*6
  833 00000020 33FFFF3C 
                       HandleBATFLT
                               EQU              IntVTAddress +4*7
  834 00000020 33FFFF40 



ARM Macro Assembler    Page 25 


                       HandleTICK
                               EQU              IntVTAddress +4*8
  835 00000020 33FFFF44 
                       HandleWDT
                               EQU              IntVTAddress +4*9
  836 00000020 33FFFF48 
                       HandleTIMER0
                               EQU              IntVTAddress +4*10
  837 00000020 33FFFF4C 
                       HandleTIMER1
                               EQU              IntVTAddress +4*11
  838 00000020 33FFFF50 
                       HandleTIMER2
                               EQU              IntVTAddress +4*12
  839 00000020 33FFFF54 
                       HandleTIMER3
                               EQU              IntVTAddress +4*13
  840 00000020 33FFFF58 
                       HandleTIMER4
                               EQU              IntVTAddress +4*14
  841 00000020 33FFFF5C 
                       HandleUART2
                               EQU              IntVTAddress +4*15
  842 00000020 33FFFF60 
                       HandleLCD
                               EQU              IntVTAddress +4*16
  843 00000020 33FFFF64 
                       HandleDMA0
                               EQU              IntVTAddress +4*17
  844 00000020 33FFFF68 
                       HandleDMA1
                               EQU              IntVTAddress +4*18
  845 00000020 33FFFF6C 
                       HandleDMA2
                               EQU              IntVTAddress +4*19
  846 00000020 33FFFF70 
                       HandleDMA3
                               EQU              IntVTAddress +4*20
  847 00000020 33FFFF74 
                       HandleMMC
                               EQU              IntVTAddress +4*21
  848 00000020 33FFFF78 
                       HandleSPI0
                               EQU              IntVTAddress +4*22
  849 00000020 33FFFF7C 
                       HandleUART1
                               EQU              IntVTAddress +4*23
  850 00000020         ;HandleReserved    EQU    IntVTAddress +4*24
  851 00000020 33FFFF84 
                       HandleUSBD
                               EQU              IntVTAddress +4*25
  852 00000020 33FFFF88 
                       HandleUSBH
                               EQU              IntVTAddress +4*26
  853 00000020 33FFFF8C 
                       HandleIIC
                               EQU              IntVTAddress +4*27
  854 00000020 33FFFF90 
                       HandleUART0



ARM Macro Assembler    Page 26 


                               EQU              IntVTAddress +4*28
  855 00000020 33FFFFBC 
                       HandleSPI1
                               EQU              IntVTAddress +4*39
  856 00000020 33FFFF98 
                       HandleRTC
                               EQU              IntVTAddress +4*30
  857 00000020 33FFFF9C 
                       HandleADC
                               EQU              IntVTAddress +4*31
  858 00000020         
  859 00000020         
  860 00000020         IRQ_Entry
  861 00000020 E24DD004        sub              sp,sp,#4    ;reserved for PC
  862 00000024 E92D0300        stmfd            sp!,{r8-r9}
  863 00000028         
  864 00000028 E59F9160        ldr              r9,=INTOFFSET
  865 0000002C E5999000        ldr              r9,[r9]
  866 00000030 E59F815C        ldr              r8,=HandleEINT0
  867 00000034 E0888109        add              r8,r8,r9,lsl #2
  868 00000038 E5988000        ldr              r8,[r8]
  869 0000003C E58D8008        str              r8,[sp,#8]
  870 00000040 E8BD8300        ldmfd            sp!,{r8-r9,pc}
  871 00000044         
  872 00000044                 ENDIF
  873 00000044         
  874 00000044 00000000 
                       Reset_Addr
                               DCD              Reset_Handler
  875 00000048 00000000 
                       Undef_Addr
                               DCD              Undef_Handler
  876 0000004C 00000000 
                       SWI_Addr
                               DCD              SWI_Handler
  877 00000050 00000000 
                       PAbt_Addr
                               DCD              PAbt_Handler
  878 00000054 00000000 
                       DAbt_Addr
                               DCD              DAbt_Handler
  879 00000058 00000000        DCD              0           ; Reserved Address 
                                                            
  880 0000005C 00000000 
                       IRQ_Addr
                               DCD              IRQ_Handler
  881 00000060 00000000 
                       FIQ_Addr
                               DCD              FIQ_Handler
  882 00000064         
  883 00000064 EAFFFFFE 
                       Undef_Handler
                               B                Undef_Handler
  884 00000068 EAFFFFFE 
                       SWI_Handler
                               B                SWI_Handler
  885 0000006C EAFFFFFE 
                       PAbt_Handler
                               B                PAbt_Handler



ARM Macro Assembler    Page 27 


  886 00000070 EAFFFFFE 
                       DAbt_Handler
                               B                DAbt_Handler
  887 00000074         
  888 00000074                 IF               IntVT_SETUP <> 1
  890                          ENDIF
  891 00000074         
  892 00000074                 IF               IntVT_SETUP <> 0
  893 00000074 EAFFFFE9 
                       IRQ_Handler
                               B                IRQ_Entry
  894 00000078                 ENDIF
  895 00000078         
  896 00000078 EAFFFFFE 
                       FIQ_Handler
                               B                FIQ_Handler
  897 0000007C         
  898 0000007C         
  899 0000007C         
  900 0000007C         ; Memory Controller Configuration
  901 0000007C                 IF               MC_SETUP <> 0
  902 0000007C         MC_CFG
  903 0000007C 22119120        DCD              BWSCON_Val
  904 00000080 00000700        DCD              BANKCON0_Val
  905 00000084 00000700        DCD              BANKCON1_Val
  906 00000088 00000700        DCD              BANKCON2_Val
  907 0000008C 00000700        DCD              BANKCON3_Val
  908 00000090 00000700        DCD              BANKCON4_Val
  909 00000094 00000700        DCD              BANKCON5_Val
  910 00000098 00018005        DCD              BANKCON6_Val
  911 0000009C 00018005        DCD              BANKCON7_Val
  912 000000A0 008E0459        DCD              REFRESH_Val
  913 000000A4 00000032        DCD              BANKSIZE_Val
  914 000000A8 00000030        DCD              MRSRB6_Val
  915 000000AC 00000030        DCD              MRSRB7_Val
  916 000000B0                 ENDIF
  917 000000B0         
  918 000000B0         
  919 000000B0         ; Clock Management Configuration
  920 000000B0                 IF               CLK_SETUP <> 0
  928                          ENDIF
  929 000000B0         
  930 000000B0         
  931 000000B0         
  932 000000B0         ; I/O Configuration
  933 000000B0                 IF               PIO_SETUP <> 0
  934 000000B0         PIOA_CFG
  935 000000B0 000003FF        DCD              PCONA_Val
  936 000000B4 000007FF 
                       PIOB_CFG
                               DCD              PCONB_Val
  937 000000B8 00000000        DCD              PUPB_Val
  938 000000BC AAAAAAAA 
                       PIOC_CFG
                               DCD              PCONC_Val
  939 000000C0 00000000        DCD              PUPC_Val
  940 000000C4 00000000 
                       PIOD_CFG
                               DCD              PCOND_Val



ARM Macro Assembler    Page 28 


  941 000000C8 00000000        DCD              PUPD_Val
  942 000000CC 00000000 
                       PIOE_CFG
                               DCD              PCONE_Val
  943 000000D0 00000000        DCD              PUPE_Val
  944 000000D4 000055AA 
                       PIOF_CFG
                               DCD              PCONF_Val
  945 000000D8 000000FF        DCD              PUPF_Val
  946 000000DC 00000000 
                       PIOG_CFG
                               DCD              PCONG_Val
  947 000000E0 00000000        DCD              PUPG_Val
  948 000000E4 000007FF 
                       PIOH_CFG
                               DCD              PCONH_Val
  949 000000E8 00000000        DCD              PUPH_Val
  950 000000EC                 ENDIF
  951 000000EC         
  952 000000EC         ; Reset Handler
  953 000000EC         
  954 000000EC                 EXPORT           Reset_Handler
  955 000000EC         Reset_Handler
  956 000000EC         
  957 000000EC                 IF               WT_SETUP <> 0
  958 000000EC E3A00453        LDR              R0, =WT_BASE
  959 000000F0 E3A01000        LDR              R1, =WTCON_Val
  960 000000F4 E3A02902        LDR              R2, =WTDAT_Val
  961 000000F8 E5802008        STR              R2, [R0, #WTCNT_OFS]
  962 000000FC E5802004        STR              R2, [R0, #WTDAT_OFS]
  963 00000100 E5801000        STR              R1, [R0, #WTCON_OFS]
  964 00000104                 ENDIF
  965 00000104         
  966 00000104                 IF               INT_SETUP <> 0
  967 00000104 E3A0044A        LDR              R0, =INT_BASE
  968 00000108 E3E01000        LDR              R1, =INTMSK_VAL
  969 0000010C E59F2084        LDR              R2, =INTSUBMASK_VAL
  970 00000110 E5801008        STR              R1, [R0,#INTMSK_OFS]
  971 00000114 E580201C        STR              R2, [R0,#INTSUBMASK_OFS]
  972 00000118                 ENDIF
  973 00000118         
  974 00000118                 IF               CLK_SETUP <> 0
  984                          ENDIF
  985 00000118         
  986 00000118         
  987 00000118                 IF               MC_SETUP <> 0
  988 00000118 E24FD0A4        ADR              R13, MC_CFG
  989 0000011C E89D1FFF        LDMIA            R13, {R0-R12}
  990 00000120 E3A0D312        LDR              R13, =MC_BASE
  991 00000124 E88D1FFF        STMIA            R13, {R0-R12}
  992 00000128                 ENDIF
  993 00000128         
  994 00000128         
  995 00000128                 IF               PIO_SETUP <> 0
  996 00000128 E3A0D456        LDR              R13, =PIO_BASE
  997 0000012C         
  998 0000012C                 IF               PIOA_SETUP <> 0
 1001                          ENDIF
 1002 0000012C         



ARM Macro Assembler    Page 29 


 1003 0000012C                 IF               PIOB_SETUP <> 0
 1008                          ENDIF
 1009 0000012C         
 1010 0000012C                 IF               PIOC_SETUP <> 0
 1015                          ENDIF
 1016 0000012C         
 1017 0000012C                 IF               PIOD_SETUP <> 0
 1022                          ENDIF
 1023 0000012C         
 1024 0000012C                 IF               PIOE_SETUP <> 0
 1029                          ENDIF
 1030 0000012C         
 1031 0000012C                 IF               PIOF_SETUP <> 0
 1032 0000012C E24F0060        ADR              R0, PIOF_CFG
 1033 00000130 E5901004        LDR              R1, [R0,#4]
 1034 00000134 E58D0050        STR              R0, [R13, #PCONF_OFS]
 1035 00000138 E58D1058        STR              R1, [R13, #PUPF_OFS]
 1036 0000013C                 ENDIF
 1037 0000013C         
 1038 0000013C                 IF               PIOG_SETUP <> 0
 1043                          ENDIF
 1044 0000013C         
 1045 0000013C                 IF               PIOH_SETUP <> 0
 1050                          ENDIF
 1051 0000013C         
 1052 0000013C                 ENDIF
 1053 0000013C         
 1054 0000013C         
 1055 0000013C         ; Setup Stack for each mode
 1056 0000013C         
 1057 0000013C E59F0058        LDR              R0, =Stack_Top
 1058 00000140         
 1059 00000140         ;  Enter Undefined Instruction Mode and set its Stack Po
                       inter
 1060 00000140 E321F0DB        MSR              CPSR_c, #Mode_UND:OR:I_Bit:OR:F
_Bit
 1061 00000144 E1A0D000        MOV              SP, R0
 1062 00000148 E2400B01        SUB              R0, R0, #UND_Stack_Size
 1063 0000014C         
 1064 0000014C         ;  Enter Abort Mode and set its Stack Pointer
 1065 0000014C E321F0D7        MSR              CPSR_c, #Mode_ABT:OR:I_Bit:OR:F
_Bit
 1066 00000150 E1A0D000        MOV              SP, R0
 1067 00000154 E2400B01        SUB              R0, R0, #ABT_Stack_Size
 1068 00000158         
 1069 00000158         ;  Enter FIQ Mode and set its Stack Pointer
 1070 00000158 E321F0D1        MSR              CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F
_Bit
 1071 0000015C E1A0D000        MOV              SP, R0
 1072 00000160 E2400A01        SUB              R0, R0, #FIQ_Stack_Size
 1073 00000164         
 1074 00000164         ;  Enter IRQ Mode and set its Stack Pointer
 1075 00000164 E321F0D2        MSR              CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F
_Bit
 1076 00000168 E1A0D000        MOV              SP, R0
 1077 0000016C E2400A01        SUB              R0, R0, #IRQ_Stack_Size
 1078 00000170         
 1079 00000170         ;  Enter Supervisor Mode and set its Stack Pointer
 1080 00000170 E321F0D3        MSR              CPSR_c, #Mode_SVC:OR:I_Bit:OR:F



ARM Macro Assembler    Page 30 


_Bit
 1081 00000174 E1A0D000        MOV              SP, R0
 1082 00000178 E2400A01        SUB              R0, R0, #SVC_Stack_Size
 1083 0000017C         
 1084 0000017C         ;  Enter User Mode and set its Stack Pointer
 1085 0000017C E321F010        MSR              CPSR_c, #Mode_USR
 1086 00000180 E1A0D000        MOV              SP, R0
 1087 00000184 E24DAB0E        SUB              SL, SP, #USR_Stack_Size
 1088 00000188         
 1089 00000188         
 1090 00000188         ; Enter the C code
 1091 00000188         
 1092 00000188                 IMPORT           __main
 1093 00000188 E59F0010        LDR              R0, =__main
 1094 0000018C E12FFF10        BX               R0
 1095 00000190         
 1096 00000190         
 1097 00000190         ; User Initial Stack & Heap
 1098 00000190 4A000014 
              33FFFF20 
              000007FF 
              00000000 
              00000000         AREA             |.text|, CODE, READONLY
 1099 00000000         
 1100 00000000                 IMPORT           __use_two_region_memory
 1101 00000000                 EXPORT           __user_initial_stackheap
 1102 00000000         __user_initial_stackheap
 1103 00000000         
 1104 00000000 E59F000C        LDR              R0, =  Heap_Mem
 1105 00000004 E59F100C        LDR              R1, =(Stack_Mem + USR_Stack_Siz
e)
 1106 00000008 E59F200C        LDR              R2, = (Heap_Mem +      Heap_Siz
e)
 1107 0000000C E59F300C        LDR              R3, = Stack_Mem
 1108 00000010 E12FFF1E        BX               LR
 1109 00000014         
 1110 00000014         
 1111 00000014                 END
              00000000 
              00003800 
              00004800 
              00000000 
Command Line: --debug --xref --device=DARMSS9 --apcs=interwork -o.\obj\S3C2410A
.o -I..\common\inc -IC:\Keil\ARM\INC\Samsung --list=.\lst\S3C2410A.lst S3C2410A
.s



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

STACK 00000000

Symbol: STACK
   Definitions
      At line 49 in file S3C2410A.s
   Uses
      None
Comment: STACK unused
Stack_Mem 00000000

Symbol: Stack_Mem
   Definitions
      At line 50 in file S3C2410A.s
   Uses
      At line 52 in file S3C2410A.s
      At line 1105 in file S3C2410A.s
      At line 1107 in file S3C2410A.s

Stack_Top 00007000

Symbol: Stack_Top
   Definitions
      At line 52 in file S3C2410A.s
   Uses
      At line 1057 in file S3C2410A.s
Comment: Stack_Top used once
3 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

HEAP 00000000

Symbol: HEAP
   Definitions
      At line 61 in file S3C2410A.s
   Uses
      None
Comment: HEAP unused
Heap_Mem 00000000

Symbol: Heap_Mem
   Definitions
      At line 62 in file S3C2410A.s
   Uses
      At line 1104 in file S3C2410A.s
      At line 1106 in file S3C2410A.s

2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

DAbt_Addr 00000054

Symbol: DAbt_Addr
   Definitions
      At line 878 in file S3C2410A.s
   Uses
      At line 817 in file S3C2410A.s
Comment: DAbt_Addr used once
DAbt_Handler 00000070

Symbol: DAbt_Handler
   Definitions
      At line 886 in file S3C2410A.s
   Uses
      At line 878 in file S3C2410A.s
      At line 886 in file S3C2410A.s

FIQ_Addr 00000060

Symbol: FIQ_Addr
   Definitions
      At line 881 in file S3C2410A.s
   Uses
      At line 820 in file S3C2410A.s
Comment: FIQ_Addr used once
FIQ_Handler 00000078

Symbol: FIQ_Handler
   Definitions
      At line 896 in file S3C2410A.s
   Uses
      At line 881 in file S3C2410A.s
      At line 896 in file S3C2410A.s

IRQ_Addr 0000005C

Symbol: IRQ_Addr
   Definitions
      At line 880 in file S3C2410A.s
   Uses
      At line 819 in file S3C2410A.s
Comment: IRQ_Addr used once
IRQ_Entry 00000020

Symbol: IRQ_Entry
   Definitions
      At line 860 in file S3C2410A.s
   Uses
      At line 893 in file S3C2410A.s
Comment: IRQ_Entry used once
IRQ_Handler 00000074

Symbol: IRQ_Handler
   Definitions
      At line 893 in file S3C2410A.s
   Uses
      At line 880 in file S3C2410A.s
Comment: IRQ_Handler used once
MC_CFG 0000007C



ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Relocatable symbols


Symbol: MC_CFG
   Definitions
      At line 902 in file S3C2410A.s
   Uses
      At line 988 in file S3C2410A.s
Comment: MC_CFG used once
PAbt_Addr 00000050

Symbol: PAbt_Addr
   Definitions
      At line 877 in file S3C2410A.s
   Uses
      At line 816 in file S3C2410A.s
Comment: PAbt_Addr used once
PAbt_Handler 0000006C

Symbol: PAbt_Handler
   Definitions
      At line 885 in file S3C2410A.s
   Uses
      At line 877 in file S3C2410A.s
      At line 885 in file S3C2410A.s

PIOA_CFG 000000B0

Symbol: PIOA_CFG
   Definitions
      At line 934 in file S3C2410A.s
   Uses
      None
Comment: PIOA_CFG unused
PIOB_CFG 000000B4

Symbol: PIOB_CFG
   Definitions
      At line 936 in file S3C2410A.s
   Uses
      None
Comment: PIOB_CFG unused
PIOC_CFG 000000BC

Symbol: PIOC_CFG
   Definitions
      At line 938 in file S3C2410A.s
   Uses
      None
Comment: PIOC_CFG unused
PIOD_CFG 000000C4

Symbol: PIOD_CFG
   Definitions
      At line 940 in file S3C2410A.s
   Uses
      None
Comment: PIOD_CFG unused
PIOE_CFG 000000CC

Symbol: PIOE_CFG



ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Relocatable symbols

   Definitions
      At line 942 in file S3C2410A.s
   Uses
      None
Comment: PIOE_CFG unused
PIOF_CFG 000000D4

Symbol: PIOF_CFG
   Definitions
      At line 944 in file S3C2410A.s
   Uses
      At line 1032 in file S3C2410A.s
Comment: PIOF_CFG used once
PIOG_CFG 000000DC

Symbol: PIOG_CFG
   Definitions
      At line 946 in file S3C2410A.s
   Uses
      None
Comment: PIOG_CFG unused
PIOH_CFG 000000E4

Symbol: PIOH_CFG
   Definitions
      At line 948 in file S3C2410A.s
   Uses
      None
Comment: PIOH_CFG unused
RESET 00000000

Symbol: RESET
   Definitions
      At line 804 in file S3C2410A.s
   Uses
      None
Comment: RESET unused
Reset_Addr 00000044

Symbol: Reset_Addr
   Definitions
      At line 874 in file S3C2410A.s
   Uses
      At line 813 in file S3C2410A.s
Comment: Reset_Addr used once
Reset_Handler 000000EC

Symbol: Reset_Handler
   Definitions
      At line 955 in file S3C2410A.s
   Uses
      At line 874 in file S3C2410A.s
      At line 954 in file S3C2410A.s

SWI_Addr 0000004C

Symbol: SWI_Addr
   Definitions
      At line 876 in file S3C2410A.s



ARM Macro Assembler    Page 4 Alphabetic symbol ordering
Relocatable symbols

   Uses
      At line 815 in file S3C2410A.s
Comment: SWI_Addr used once
SWI_Handler 00000068

Symbol: SWI_Handler
   Definitions
      At line 884 in file S3C2410A.s
   Uses
      At line 876 in file S3C2410A.s
      At line 884 in file S3C2410A.s

Undef_Addr 00000048

Symbol: Undef_Addr
   Definitions
      At line 875 in file S3C2410A.s
   Uses
      At line 814 in file S3C2410A.s
Comment: Undef_Addr used once
Undef_Handler 00000064

Symbol: Undef_Handler
   Definitions
      At line 883 in file S3C2410A.s
   Uses
      At line 875 in file S3C2410A.s
      At line 883 in file S3C2410A.s

Vectors 00000000

Symbol: Vectors
   Definitions
      At line 813 in file S3C2410A.s
   Uses
      None
Comment: Vectors unused
26 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.text 00000000

Symbol: .text
   Definitions
      At line 1098 in file S3C2410A.s
   Uses
      None
Comment: .text unused
__user_initial_stackheap 00000000

Symbol: __user_initial_stackheap
   Definitions
      At line 1102 in file S3C2410A.s
   Uses
      At line 1101 in file S3C2410A.s
Comment: __user_initial_stackheap used once
2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_info$$$RESET 00000000

Symbol: .debug_info$$$RESET
   Definitions
      None
   Uses
      None
Warning: .debug_info$$$RESET undefinedComment: .debug_info$$$RESET unused
1 symbol



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_line$$$RESET 00000000

Symbol: .debug_line$$$RESET
   Definitions
      None
   Uses
      None
Warning: .debug_line$$$RESET undefinedComment: .debug_line$$$RESET unused
1 symbol



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_info$$$.text 00000000

Symbol: .debug_info$$$.text
   Definitions
      None
   Uses
      None
Warning: .debug_info$$$.text undefinedComment: .debug_info$$$.text unused
1 symbol



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_line$$$.text 00000000

Symbol: .debug_line$$$.text
   Definitions
      None
   Uses
      None
Warning: .debug_line$$$.text undefinedComment: .debug_line$$$.text unused
1 symbol



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_abbrev 00000000

Symbol: .debug_abbrev
   Definitions
      None
   Uses
      None
Warning: .debug_abbrev undefinedComment: .debug_abbrev unused
__ARM_asm.debug_abbrev 00000000

Symbol: __ARM_asm.debug_abbrev
   Definitions
      None
   Uses
      None
Warning: __ARM_asm.debug_abbrev undefinedComment: __ARM_asm.debug_abbrev unused
2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Absolute symbols

ABT_Stack_Size 00000400

Symbol: ABT_Stack_Size
   Definitions
      At line 41 in file S3C2410A.s
   Uses
      At line 47 in file S3C2410A.s
      At line 1067 in file S3C2410A.s

BANKCON0_Val 00000700

Symbol: BANKCON0_Val
   Definitions
      At line 479 in file S3C2410A.s
   Uses
      At line 904 in file S3C2410A.s
Comment: BANKCON0_Val used once
BANKCON1_Val 00000700

Symbol: BANKCON1_Val
   Definitions
      At line 480 in file S3C2410A.s
   Uses
      At line 905 in file S3C2410A.s
Comment: BANKCON1_Val used once
BANKCON2_Val 00000700

Symbol: BANKCON2_Val
   Definitions
      At line 481 in file S3C2410A.s
   Uses
      At line 906 in file S3C2410A.s
Comment: BANKCON2_Val used once
BANKCON3_Val 00000700

Symbol: BANKCON3_Val
   Definitions
      At line 482 in file S3C2410A.s
   Uses
      At line 907 in file S3C2410A.s
Comment: BANKCON3_Val used once
BANKCON4_Val 00000700

Symbol: BANKCON4_Val
   Definitions
      At line 483 in file S3C2410A.s
   Uses
      At line 908 in file S3C2410A.s
Comment: BANKCON4_Val used once
BANKCON5_Val 00000700

Symbol: BANKCON5_Val
   Definitions
      At line 484 in file S3C2410A.s
   Uses
      At line 909 in file S3C2410A.s
Comment: BANKCON5_Val used once
BANKCON6_Val 00018005




ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Absolute symbols

Symbol: BANKCON6_Val
   Definitions
      At line 485 in file S3C2410A.s
   Uses
      At line 910 in file S3C2410A.s
Comment: BANKCON6_Val used once
BANKCON7_Val 00018005

Symbol: BANKCON7_Val
   Definitions
      At line 486 in file S3C2410A.s
   Uses
      At line 911 in file S3C2410A.s
Comment: BANKCON7_Val used once
BANKSIZE_Val 00000032

Symbol: BANKSIZE_Val
   Definitions
      At line 489 in file S3C2410A.s
   Uses
      At line 913 in file S3C2410A.s
Comment: BANKSIZE_Val used once
BWSCON_Val 22119120

Symbol: BWSCON_Val
   Definitions
      At line 487 in file S3C2410A.s
   Uses
      At line 903 in file S3C2410A.s
Comment: BWSCON_Val used once
CAMDIVN_OFS 00000018

Symbol: CAMDIVN_OFS
   Definitions
      At line 85 in file S3C2410A.s
   Uses
      None
Comment: CAMDIVN_OFS unused
CLKCON_OFS 0000000C

Symbol: CLKCON_OFS
   Definitions
      At line 82 in file S3C2410A.s
   Uses
      None
Comment: CLKCON_OFS unused
CLKCON_Val 0007FFF0

Symbol: CLKCON_Val
   Definitions
      At line 153 in file S3C2410A.s
   Uses
      None
Comment: CLKCON_Val unused
CLKDIVN_OFS 00000014

Symbol: CLKDIVN_OFS
   Definitions
      At line 84 in file S3C2410A.s



ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Absolute symbols

   Uses
      None
Comment: CLKDIVN_OFS unused
CLKDIVN_Val 00000003

Symbol: CLKDIVN_Val
   Definitions
      At line 156 in file S3C2410A.s
   Uses
      None
Comment: CLKDIVN_Val unused
CLKSLOW_OFS 00000010

Symbol: CLKSLOW_OFS
   Definitions
      At line 83 in file S3C2410A.s
   Uses
      None
Comment: CLKSLOW_OFS unused
CLKSLOW_Val 00000004

Symbol: CLKSLOW_Val
   Definitions
      At line 154 in file S3C2410A.s
   Uses
      None
Comment: CLKSLOW_Val unused
CLK_BASE 4C000000

Symbol: CLK_BASE
   Definitions
      At line 78 in file S3C2410A.s
   Uses
      None
Comment: CLK_BASE unused
CLK_SETUP 00000000

Symbol: CLK_SETUP
   Definitions
      At line 150 in file S3C2410A.s
   Uses
      At line 920 in file S3C2410A.s
      At line 974 in file S3C2410A.s

FIQ_Stack_Size 00001000

Symbol: FIQ_Stack_Size
   Definitions
      At line 42 in file S3C2410A.s
   Uses
      At line 47 in file S3C2410A.s
      At line 1072 in file S3C2410A.s

F_Bit 00000040

Symbol: F_Bit
   Definitions
      At line 28 in file S3C2410A.s
   Uses



ARM Macro Assembler    Page 4 Alphabetic symbol ordering
Absolute symbols

      At line 1060 in file S3C2410A.s
      At line 1065 in file S3C2410A.s
      At line 1070 in file S3C2410A.s
      At line 1075 in file S3C2410A.s
      At line 1080 in file S3C2410A.s

HandleADC 33FFFF9C

Symbol: HandleADC
   Definitions
      At line 857 in file S3C2410A.s
   Uses
      None
Comment: HandleADC unused
HandleBATFLT 33FFFF3C

Symbol: HandleBATFLT
   Definitions
      At line 833 in file S3C2410A.s
   Uses
      None
Comment: HandleBATFLT unused
HandleDMA0 33FFFF64

Symbol: HandleDMA0
   Definitions
      At line 843 in file S3C2410A.s
   Uses
      None
Comment: HandleDMA0 unused
HandleDMA1 33FFFF68

Symbol: HandleDMA1
   Definitions
      At line 844 in file S3C2410A.s
   Uses
      None
Comment: HandleDMA1 unused
HandleDMA2 33FFFF6C

Symbol: HandleDMA2
   Definitions
      At line 845 in file S3C2410A.s
   Uses
      None
Comment: HandleDMA2 unused
HandleDMA3 33FFFF70

Symbol: HandleDMA3
   Definitions
      At line 846 in file S3C2410A.s
   Uses
      None
Comment: HandleDMA3 unused
HandleEINT0 33FFFF20

Symbol: HandleEINT0
   Definitions
      At line 826 in file S3C2410A.s



ARM Macro Assembler    Page 5 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 866 in file S3C2410A.s
Comment: HandleEINT0 used once
HandleEINT1 33FFFF24

Symbol: HandleEINT1
   Definitions
      At line 827 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT1 unused
HandleEINT2 33FFFF28

Symbol: HandleEINT2
   Definitions
      At line 828 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT2 unused
HandleEINT3 33FFFF2C

Symbol: HandleEINT3
   Definitions
      At line 829 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT3 unused
HandleEINT4_7 33FFFF30

Symbol: HandleEINT4_7
   Definitions
      At line 830 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT4_7 unused
HandleEINT8_23 33FFFF34

Symbol: HandleEINT8_23
   Definitions
      At line 831 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT8_23 unused
HandleIIC 33FFFF8C

Symbol: HandleIIC
   Definitions
      At line 853 in file S3C2410A.s
   Uses
      None
Comment: HandleIIC unused
HandleLCD 33FFFF60

Symbol: HandleLCD
   Definitions
      At line 842 in file S3C2410A.s
   Uses
      None
Comment: HandleLCD unused



ARM Macro Assembler    Page 6 Alphabetic symbol ordering
Absolute symbols

HandleMMC 33FFFF74

Symbol: HandleMMC
   Definitions
      At line 847 in file S3C2410A.s
   Uses
      None
Comment: HandleMMC unused
HandleRTC 33FFFF98

Symbol: HandleRTC
   Definitions
      At line 856 in file S3C2410A.s
   Uses
      None
Comment: HandleRTC unused
HandleReserved 33FFFF38

Symbol: HandleReserved
   Definitions
      At line 832 in file S3C2410A.s
   Uses
      None
Comment: HandleReserved unused
HandleSPI0 33FFFF78

Symbol: HandleSPI0
   Definitions
      At line 848 in file S3C2410A.s
   Uses
      None
Comment: HandleSPI0 unused
HandleSPI1 33FFFFBC

Symbol: HandleSPI1
   Definitions
      At line 855 in file S3C2410A.s
   Uses
      None
Comment: HandleSPI1 unused
HandleTICK 33FFFF40

Symbol: HandleTICK
   Definitions
      At line 834 in file S3C2410A.s
   Uses
      None
Comment: HandleTICK unused
HandleTIMER0 33FFFF48

Symbol: HandleTIMER0
   Definitions
      At line 836 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER0 unused
HandleTIMER1 33FFFF4C

Symbol: HandleTIMER1



ARM Macro Assembler    Page 7 Alphabetic symbol ordering
Absolute symbols

   Definitions
      At line 837 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER1 unused
HandleTIMER2 33FFFF50

Symbol: HandleTIMER2
   Definitions
      At line 838 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER2 unused
HandleTIMER3 33FFFF54

Symbol: HandleTIMER3
   Definitions
      At line 839 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER3 unused
HandleTIMER4 33FFFF58

Symbol: HandleTIMER4
   Definitions
      At line 840 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER4 unused
HandleUART0 33FFFF90

Symbol: HandleUART0
   Definitions
      At line 854 in file S3C2410A.s
   Uses
      None
Comment: HandleUART0 unused
HandleUART1 33FFFF7C

Symbol: HandleUART1
   Definitions
      At line 849 in file S3C2410A.s
   Uses
      None
Comment: HandleUART1 unused
HandleUART2 33FFFF5C

Symbol: HandleUART2
   Definitions
      At line 841 in file S3C2410A.s
   Uses
      None
Comment: HandleUART2 unused
HandleUSBD 33FFFF84

Symbol: HandleUSBD
   Definitions
      At line 851 in file S3C2410A.s
   Uses



ARM Macro Assembler    Page 8 Alphabetic symbol ordering
Absolute symbols

      None
Comment: HandleUSBD unused
HandleUSBH 33FFFF88

Symbol: HandleUSBH
   Definitions
      At line 852 in file S3C2410A.s
   Uses
      None
Comment: HandleUSBH unused
HandleWDT 33FFFF44

Symbol: HandleWDT
   Definitions
      At line 835 in file S3C2410A.s
   Uses
      None
Comment: HandleWDT unused
Heap_Size 00004800

Symbol: Heap_Size
   Definitions
      At line 59 in file S3C2410A.s
   Uses
      At line 62 in file S3C2410A.s
      At line 1106 in file S3C2410A.s

INTMSK_OFS 00000008

Symbol: INTMSK_OFS
   Definitions
      At line 68 in file S3C2410A.s
   Uses
      At line 970 in file S3C2410A.s
Comment: INTMSK_OFS used once
INTMSK_VAL FFFFFFFF

Symbol: INTMSK_VAL
   Definitions
      At line 73 in file S3C2410A.s
   Uses
      At line 968 in file S3C2410A.s
Comment: INTMSK_VAL used once
INTOFFSET 4A000014

Symbol: INTOFFSET
   Definitions
      At line 161 in file S3C2410A.s
   Uses
      At line 864 in file S3C2410A.s
Comment: INTOFFSET used once
INTPND_OFS 00000010

Symbol: INTPND_OFS
   Definitions
      At line 69 in file S3C2410A.s
   Uses
      None
Comment: INTPND_OFS unused



ARM Macro Assembler    Page 9 Alphabetic symbol ordering
Absolute symbols

INTSUBMASK_OFS 0000001C

Symbol: INTSUBMASK_OFS
   Definitions
      At line 70 in file S3C2410A.s
   Uses
      At line 971 in file S3C2410A.s
Comment: INTSUBMASK_OFS used once
INTSUBMASK_VAL 000007FF

Symbol: INTSUBMASK_VAL
   Definitions
      At line 74 in file S3C2410A.s
   Uses
      At line 969 in file S3C2410A.s
Comment: INTSUBMASK_VAL used once
INT_BASE 4A000000

Symbol: INT_BASE
   Definitions
      At line 66 in file S3C2410A.s
   Uses
      At line 967 in file S3C2410A.s
Comment: INT_BASE used once
INT_SETUP 00000001

Symbol: INT_SETUP
   Definitions
      At line 72 in file S3C2410A.s
   Uses
      At line 966 in file S3C2410A.s
Comment: INT_SETUP used once
IRQ_Stack_Size 00001000

Symbol: IRQ_Stack_Size
   Definitions
      At line 43 in file S3C2410A.s
   Uses
      At line 47 in file S3C2410A.s
      At line 1077 in file S3C2410A.s

I_Bit 00000080

Symbol: I_Bit
   Definitions
      At line 27 in file S3C2410A.s
   Uses
      At line 1060 in file S3C2410A.s
      At line 1065 in file S3C2410A.s
      At line 1070 in file S3C2410A.s
      At line 1075 in file S3C2410A.s
      At line 1080 in file S3C2410A.s

IntVTAddress 33FFFF20

Symbol: IntVTAddress
   Definitions
      At line 169 in file S3C2410A.s
   Uses



ARM Macro Assembler    Page 10 Alphabetic symbol ordering
Absolute symbols

      At line 826 in file S3C2410A.s
      At line 827 in file S3C2410A.s
      At line 828 in file S3C2410A.s
      At line 829 in file S3C2410A.s
      At line 830 in file S3C2410A.s
      At line 831 in file S3C2410A.s
      At line 832 in file S3C2410A.s
      At line 833 in file S3C2410A.s
      At line 834 in file S3C2410A.s
      At line 835 in file S3C2410A.s
      At line 836 in file S3C2410A.s
      At line 837 in file S3C2410A.s
      At line 838 in file S3C2410A.s
      At line 839 in file S3C2410A.s
      At line 840 in file S3C2410A.s
      At line 841 in file S3C2410A.s
      At line 842 in file S3C2410A.s
      At line 843 in file S3C2410A.s
      At line 844 in file S3C2410A.s
      At line 845 in file S3C2410A.s
      At line 846 in file S3C2410A.s
      At line 847 in file S3C2410A.s
      At line 848 in file S3C2410A.s
      At line 849 in file S3C2410A.s
      At line 851 in file S3C2410A.s
      At line 852 in file S3C2410A.s
      At line 853 in file S3C2410A.s
      At line 854 in file S3C2410A.s
      At line 855 in file S3C2410A.s
      At line 856 in file S3C2410A.s
      At line 857 in file S3C2410A.s

IntVT_SETUP 00000001

Symbol: IntVT_SETUP
   Definitions
      At line 168 in file S3C2410A.s
   Uses
      At line 823 in file S3C2410A.s
      At line 888 in file S3C2410A.s
      At line 892 in file S3C2410A.s

LOCKTIME_OFS 00000000

Symbol: LOCKTIME_OFS
   Definitions
      At line 79 in file S3C2410A.s
   Uses
      None
Comment: LOCKTIME_OFS unused
LOCKTIME_Val 00FFFFFF

Symbol: LOCKTIME_Val
   Definitions
      At line 155 in file S3C2410A.s
   Uses
      None
Comment: LOCKTIME_Val unused
MC_BASE 48000000



ARM Macro Assembler    Page 11 Alphabetic symbol ordering
Absolute symbols


Symbol: MC_BASE
   Definitions
      At line 193 in file S3C2410A.s
   Uses
      At line 990 in file S3C2410A.s
Comment: MC_BASE used once
MC_SETUP 00000001

Symbol: MC_SETUP
   Definitions
      At line 196 in file S3C2410A.s
   Uses
      At line 901 in file S3C2410A.s
      At line 987 in file S3C2410A.s

MPLLCON_OFS 00000004

Symbol: MPLLCON_OFS
   Definitions
      At line 80 in file S3C2410A.s
   Uses
      None
Comment: MPLLCON_OFS unused
MPLLCON_Val 0005C042

Symbol: MPLLCON_Val
   Definitions
      At line 151 in file S3C2410A.s
   Uses
      None
Comment: MPLLCON_Val unused
MRSRB6_Val 00000030

Symbol: MRSRB6_Val
   Definitions
      At line 490 in file S3C2410A.s
   Uses
      At line 914 in file S3C2410A.s
Comment: MRSRB6_Val used once
MRSRB7_Val 00000030

Symbol: MRSRB7_Val
   Definitions
      At line 491 in file S3C2410A.s
   Uses
      At line 915 in file S3C2410A.s
Comment: MRSRB7_Val used once
Mode_ABT 00000017

Symbol: Mode_ABT
   Definitions
      At line 23 in file S3C2410A.s
   Uses
      At line 1065 in file S3C2410A.s
Comment: Mode_ABT used once
Mode_FIQ 00000011

Symbol: Mode_FIQ



ARM Macro Assembler    Page 12 Alphabetic symbol ordering
Absolute symbols

   Definitions
      At line 20 in file S3C2410A.s
   Uses
      At line 1070 in file S3C2410A.s
Comment: Mode_FIQ used once
Mode_IRQ 00000012

Symbol: Mode_IRQ
   Definitions
      At line 21 in file S3C2410A.s
   Uses
      At line 1075 in file S3C2410A.s
Comment: Mode_IRQ used once
Mode_SVC 00000013

Symbol: Mode_SVC
   Definitions
      At line 22 in file S3C2410A.s
   Uses
      At line 1080 in file S3C2410A.s
Comment: Mode_SVC used once
Mode_SYS 0000001F

Symbol: Mode_SYS
   Definitions
      At line 25 in file S3C2410A.s
   Uses
      None
Comment: Mode_SYS unused
Mode_UND 0000001B

Symbol: Mode_UND
   Definitions
      At line 24 in file S3C2410A.s
   Uses
      At line 1060 in file S3C2410A.s
Comment: Mode_UND used once
Mode_USR 00000010

Symbol: Mode_USR
   Definitions
      At line 19 in file S3C2410A.s
   Uses
      At line 1085 in file S3C2410A.s
Comment: Mode_USR used once
PCONA_OFS 00000000

Symbol: PCONA_OFS
   Definitions
      At line 499 in file S3C2410A.s
   Uses
      None
Comment: PCONA_OFS unused
PCONA_Val 000003FF

Symbol: PCONA_Val
   Definitions
      At line 547 in file S3C2410A.s
   Uses



ARM Macro Assembler    Page 13 Alphabetic symbol ordering
Absolute symbols

      At line 935 in file S3C2410A.s
Comment: PCONA_Val used once
PCONB_OFS 00000010

Symbol: PCONB_OFS
   Definitions
      At line 500 in file S3C2410A.s
   Uses
      None
Comment: PCONB_OFS unused
PCONB_Val 000007FF

Symbol: PCONB_Val
   Definitions
      At line 576 in file S3C2410A.s
   Uses
      At line 936 in file S3C2410A.s
Comment: PCONB_Val used once
PCONC_OFS 00000020

Symbol: PCONC_OFS
   Definitions
      At line 501 in file S3C2410A.s
   Uses
      None
Comment: PCONC_OFS unused
PCONC_Val AAAAAAAA

Symbol: PCONC_Val
   Definitions
      At line 616 in file S3C2410A.s
   Uses
      At line 938 in file S3C2410A.s
Comment: PCONC_Val used once
PCOND_OFS 00000030

Symbol: PCOND_OFS
   Definitions
      At line 502 in file S3C2410A.s
   Uses
      None
Comment: PCOND_OFS unused
PCOND_Val 00000000

Symbol: PCOND_Val
   Definitions
      At line 656 in file S3C2410A.s
   Uses
      At line 940 in file S3C2410A.s
Comment: PCOND_Val used once
PCONE_OFS 00000040

Symbol: PCONE_OFS
   Definitions
      At line 503 in file S3C2410A.s
   Uses
      None
Comment: PCONE_OFS unused
PCONE_Val 00000000



ARM Macro Assembler    Page 14 Alphabetic symbol ordering
Absolute symbols


Symbol: PCONE_Val
   Definitions
      At line 696 in file S3C2410A.s
   Uses
      At line 942 in file S3C2410A.s
Comment: PCONE_Val used once
PCONF_OFS 00000050

Symbol: PCONF_OFS
   Definitions
      At line 504 in file S3C2410A.s
   Uses
      At line 1034 in file S3C2410A.s
Comment: PCONF_OFS used once
PCONF_Val 000055AA

Symbol: PCONF_Val
   Definitions
      At line 720 in file S3C2410A.s
   Uses
      At line 944 in file S3C2410A.s
Comment: PCONF_Val used once
PCONG_OFS 00000060

Symbol: PCONG_OFS
   Definitions
      At line 505 in file S3C2410A.s
   Uses
      None
Comment: PCONG_OFS unused
PCONG_Val 00000000

Symbol: PCONG_Val
   Definitions
      At line 760 in file S3C2410A.s
   Uses
      At line 946 in file S3C2410A.s
Comment: PCONG_Val used once
PCONH_OFS 00000070

Symbol: PCONH_OFS
   Definitions
      At line 506 in file S3C2410A.s
   Uses
      None
Comment: PCONH_OFS unused
PCONH_Val 000007FF

Symbol: PCONH_Val
   Definitions
      At line 790 in file S3C2410A.s
   Uses
      At line 948 in file S3C2410A.s
Comment: PCONH_Val used once
PCONJ_OFS 000000D0

Symbol: PCONJ_OFS
   Definitions



ARM Macro Assembler    Page 15 Alphabetic symbol ordering
Absolute symbols

      At line 507 in file S3C2410A.s
   Uses
      None
Comment: PCONJ_OFS unused
PIOA_SETUP 00000000

Symbol: PIOA_SETUP
   Definitions
      At line 546 in file S3C2410A.s
   Uses
      At line 998 in file S3C2410A.s
Comment: PIOA_SETUP used once
PIOB_SETUP 00000000

Symbol: PIOB_SETUP
   Definitions
      At line 575 in file S3C2410A.s
   Uses
      At line 1003 in file S3C2410A.s
Comment: PIOB_SETUP used once
PIOC_SETUP 00000000

Symbol: PIOC_SETUP
   Definitions
      At line 615 in file S3C2410A.s
   Uses
      At line 1010 in file S3C2410A.s
Comment: PIOC_SETUP used once
PIOD_SETUP 00000000

Symbol: PIOD_SETUP
   Definitions
      At line 655 in file S3C2410A.s
   Uses
      At line 1017 in file S3C2410A.s
Comment: PIOD_SETUP used once
PIOE_SETUP 00000000

Symbol: PIOE_SETUP
   Definitions
      At line 695 in file S3C2410A.s
   Uses
      At line 1024 in file S3C2410A.s
Comment: PIOE_SETUP used once
PIOF_SETUP 00000001

Symbol: PIOF_SETUP
   Definitions
      At line 719 in file S3C2410A.s
   Uses
      At line 1031 in file S3C2410A.s
Comment: PIOF_SETUP used once
PIOG_SETUP 00000000

Symbol: PIOG_SETUP
   Definitions
      At line 759 in file S3C2410A.s
   Uses
      At line 1038 in file S3C2410A.s



ARM Macro Assembler    Page 16 Alphabetic symbol ordering
Absolute symbols

Comment: PIOG_SETUP used once
PIOH_SETUP 00000000

Symbol: PIOH_SETUP
   Definitions
      At line 789 in file S3C2410A.s
   Uses
      At line 1045 in file S3C2410A.s
Comment: PIOH_SETUP used once
PIO_BASE 56000000

Symbol: PIO_BASE
   Definitions
      At line 498 in file S3C2410A.s
   Uses
      At line 996 in file S3C2410A.s
Comment: PIO_BASE used once
PIO_SETUP 00000001

Symbol: PIO_SETUP
   Definitions
      At line 519 in file S3C2410A.s
   Uses
      At line 933 in file S3C2410A.s
      At line 995 in file S3C2410A.s

PUPB_OFS 00000018

Symbol: PUPB_OFS
   Definitions
      At line 508 in file S3C2410A.s
   Uses
      None
Comment: PUPB_OFS unused
PUPB_Val 00000000

Symbol: PUPB_Val
   Definitions
      At line 577 in file S3C2410A.s
   Uses
      At line 937 in file S3C2410A.s
Comment: PUPB_Val used once
PUPC_OFS 00000028

Symbol: PUPC_OFS
   Definitions
      At line 509 in file S3C2410A.s
   Uses
      None
Comment: PUPC_OFS unused
PUPC_Val 00000000

Symbol: PUPC_Val
   Definitions
      At line 617 in file S3C2410A.s
   Uses
      At line 939 in file S3C2410A.s
Comment: PUPC_Val used once
PUPD_OFS 00000038



ARM Macro Assembler    Page 17 Alphabetic symbol ordering
Absolute symbols


Symbol: PUPD_OFS
   Definitions
      At line 510 in file S3C2410A.s
   Uses
      None
Comment: PUPD_OFS unused
PUPD_Val 00000000

Symbol: PUPD_Val
   Definitions
      At line 657 in file S3C2410A.s
   Uses
      At line 941 in file S3C2410A.s
Comment: PUPD_Val used once
PUPE_OFS 00000048

Symbol: PUPE_OFS
   Definitions
      At line 511 in file S3C2410A.s
   Uses
      None
Comment: PUPE_OFS unused
PUPE_Val 00000000

Symbol: PUPE_Val
   Definitions
      At line 697 in file S3C2410A.s
   Uses
      At line 943 in file S3C2410A.s
Comment: PUPE_Val used once
PUPF_OFS 00000058

Symbol: PUPF_OFS
   Definitions
      At line 512 in file S3C2410A.s
   Uses
      At line 1035 in file S3C2410A.s
Comment: PUPF_OFS used once
PUPF_Val 000000FF

Symbol: PUPF_Val
   Definitions
      At line 721 in file S3C2410A.s
   Uses
      At line 945 in file S3C2410A.s
Comment: PUPF_Val used once
PUPG_OFS 00000068

Symbol: PUPG_OFS
   Definitions
      At line 513 in file S3C2410A.s
   Uses
      None
Comment: PUPG_OFS unused
PUPG_Val 00000000

Symbol: PUPG_Val
   Definitions



ARM Macro Assembler    Page 18 Alphabetic symbol ordering
Absolute symbols

      At line 761 in file S3C2410A.s
   Uses
      At line 947 in file S3C2410A.s
Comment: PUPG_Val used once
PUPH_OFS 00000078

Symbol: PUPH_OFS
   Definitions
      At line 514 in file S3C2410A.s
   Uses
      None
Comment: PUPH_OFS unused
PUPH_Val 00000000

Symbol: PUPH_Val
   Definitions
      At line 791 in file S3C2410A.s
   Uses
      At line 949 in file S3C2410A.s
Comment: PUPH_Val used once
PUPJ_OFS 000000D8

Symbol: PUPJ_OFS
   Definitions
      At line 515 in file S3C2410A.s
   Uses
      None
Comment: PUPJ_OFS unused
REFRESH_Val 008E0459

Symbol: REFRESH_Val
   Definitions
      At line 488 in file S3C2410A.s
   Uses
      At line 912 in file S3C2410A.s
Comment: REFRESH_Val used once
SRCPND_OFS 00000000

Symbol: SRCPND_OFS
   Definitions
      At line 67 in file S3C2410A.s
   Uses
      None
Comment: SRCPND_OFS unused
SVC_Stack_Size 00001000

Symbol: SVC_Stack_Size
   Definitions
      At line 40 in file S3C2410A.s
   Uses
      At line 47 in file S3C2410A.s
      At line 1082 in file S3C2410A.s

Stack_Size 00007000

Symbol: Stack_Size
   Definitions
      At line 47 in file S3C2410A.s
   Uses



ARM Macro Assembler    Page 19 Alphabetic symbol ordering
Absolute symbols

      At line 50 in file S3C2410A.s
      At line 52 in file S3C2410A.s

UND_Stack_Size 00000400

Symbol: UND_Stack_Size
   Definitions
      At line 39 in file S3C2410A.s
   Uses
      At line 47 in file S3C2410A.s
      At line 1062 in file S3C2410A.s

UPLLCON_OFS 00000008

Symbol: UPLLCON_OFS
   Definitions
      At line 81 in file S3C2410A.s
   Uses
      None
Comment: UPLLCON_OFS unused
UPLLCON_Val 00028080

Symbol: UPLLCON_Val
   Definitions
      At line 152 in file S3C2410A.s
   Uses
      None
Comment: UPLLCON_Val unused
USR_Stack_Size 00003800

Symbol: USR_Stack_Size
   Definitions
      At line 44 in file S3C2410A.s
   Uses
      At line 47 in file S3C2410A.s
      At line 1087 in file S3C2410A.s
      At line 1105 in file S3C2410A.s

WTCNT_OFS 00000008

Symbol: WTCNT_OFS
   Definitions
      At line 175 in file S3C2410A.s
   Uses
      At line 961 in file S3C2410A.s
Comment: WTCNT_OFS used once
WTCON_OFS 00000000

Symbol: WTCON_OFS
   Definitions
      At line 173 in file S3C2410A.s
   Uses
      At line 963 in file S3C2410A.s
Comment: WTCON_OFS used once
WTCON_Val 00000000

Symbol: WTCON_Val
   Definitions
      At line 188 in file S3C2410A.s



ARM Macro Assembler    Page 20 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 959 in file S3C2410A.s
Comment: WTCON_Val used once
WTDAT_OFS 00000004

Symbol: WTDAT_OFS
   Definitions
      At line 174 in file S3C2410A.s
   Uses
      At line 962 in file S3C2410A.s
Comment: WTDAT_OFS used once
WTDAT_Val 00008000

Symbol: WTDAT_Val
   Definitions
      At line 189 in file S3C2410A.s
   Uses
      At line 960 in file S3C2410A.s
Comment: WTDAT_Val used once
WT_BASE 53000000

Symbol: WT_BASE
   Definitions
      At line 172 in file S3C2410A.s
   Uses
      At line 958 in file S3C2410A.s
Comment: WT_BASE used once
WT_SETUP 00000001

Symbol: WT_SETUP
   Definitions
      At line 187 in file S3C2410A.s
   Uses
      At line 957 in file S3C2410A.s
Comment: WT_SETUP used once
138 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
External symbols

__main 00000000

Symbol: __main
   Definitions
      At line 1092 in file S3C2410A.s
   Uses
      At line 1093 in file S3C2410A.s
Comment: __main used once
__use_two_region_memory 00000000

Symbol: __use_two_region_memory
   Definitions
      At line 1100 in file S3C2410A.s
   Uses
      None
Comment: __use_two_region_memory unused
2 symbols
502 symbols in table
