


ARM Macro Assembler    Page 1 


    1 00000000         ;/******************************************************
                       ***********************/
    2 00000000         ;/* S3C2440A.S: Startup file for Samsung S3C440A        
                                             */
    3 00000000         ;/******************************************************
                       ***********************/
    4 00000000         ;/* <<< Use Configuration Wizard in Context Menu >>>    
                                             */ 
    5 00000000         ;/******************************************************
                       ***********************/
    6 00000000         ;/* This file is part of the uVision/ARM development too
                       ls.                   */
    7 00000000         ;/* Copyright (c) 2005-2006 Keil Software. All rights re
                       served.               */
    8 00000000         ;/* This software may only be used under the terms of a 
                       valid, current,       */
    9 00000000         ;/* end user licence from KEIL for a compatible version 
                       of KEIL software      */
   10 00000000         ;/* development tools. Nothing else gives you the right 
                       to use this software. */
   11 00000000         ;/******************************************************
                       ***********************/
   12 00000000         
   13 00000000         
   14 00000000         ; *** Startup Code (executed after Reset) ***
   15 00000000         
   16 00000000         
   17 00000000         ; Standard definitions of Mode bits and Interrupt (I & F
                       ) flags in PSRs
   18 00000000         
   19 00000000 00000010 
                       Mode_USR
                               EQU              0x10
   20 00000000 00000011 
                       Mode_FIQ
                               EQU              0x11
   21 00000000 00000012 
                       Mode_IRQ
                               EQU              0x12
   22 00000000 00000013 
                       Mode_SVC
                               EQU              0x13
   23 00000000 00000017 
                       Mode_ABT
                               EQU              0x17
   24 00000000 0000001B 
                       Mode_UND
                               EQU              0x1B
   25 00000000 0000001F 
                       Mode_SYS
                               EQU              0x1F
   26 00000000         
   27 00000000 00000080 
                       I_Bit   EQU              0x80        ; when I bit is set
                                                            , IRQ is disabled
   28 00000000 00000040 
                       F_Bit   EQU              0x40        ; when F bit is set
                                                            , FIQ is disabled
   29 00000000         



ARM Macro Assembler    Page 2 


   30 00000000         
   31 00000000         ;// <h> Stack Configuration (Stack Sizes in Bytes)
   32 00000000         ;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
   33 00000000         ;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
   34 00000000         ;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
   35 00000000         ;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
   36 00000000         ;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
   37 00000000         ;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
   38 00000000         ;// </h>
   39 00000000         
   40 00000000 00000400 
                       UND_Stack_Size
                               EQU              0x00000400
   41 00000000 00001000 
                       SVC_Stack_Size
                               EQU              0x00001000
   42 00000000 00000400 
                       ABT_Stack_Size
                               EQU              0x00000400
   43 00000000 00001000 
                       FIQ_Stack_Size
                               EQU              0x00001000
   44 00000000 00001000 
                       IRQ_Stack_Size
                               EQU              0x00001000
   45 00000000 00001000 
                       USR_Stack_Size
                               EQU              0x00001000
   46 00000000         
   48 00000000 00004800 
                       Stack_Size
                               EQU              (UND_Stack_Size + SVC_Stack_Siz
e + ABT_Stack_Size +                           FIQ_Stack_Size + IRQ_Stack_Size
 + USR_Stack_Size)
   49 00000000         
   50 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
=3
   51 00000000         Stack_Mem
                               SPACE            Stack_Size
   52 00004800         
   53 00004800 00004800 
                       Stack_Top
                               EQU              Stack_Mem + Stack_Size
   54 00004800         
   55 00004800         
   56 00004800         ;// <h> Heap Configuration
   57 00004800         ;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
   58 00004800         ;// </h>
   59 00004800         
   60 00004800 00002000 
                       Heap_Size
                               EQU              0x00002000
   61 00004800         
   62 00004800                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
3
   63 00000000         Heap_Mem
                               SPACE            Heap_Size
   64 00002000         
   65 00002000         ;INT CONFIG



ARM Macro Assembler    Page 3 


   66 00002000 4A000000 
                       INT_BASE
                               EQU              0X4A000000
   67 00002000 00000008 
                       INTMASK_OFS
                               EQU              0X08
   68 00002000 0000001C 
                       INTSUBMASK_OFS
                               EQU              0X1C
   69 00002000         
   70 00002000 00000001 
                       INT_SETUP
                               EQU              1
   71 00002000 FFFFFFFF 
                       INTMASK_VAL
                               EQU              0XFFFFFFFF
   72 00002000 000007FF 
                       INTSUBMASK_VAL
                               EQU              0X7FF
   73 00002000         
   74 00002000         ; Clock Management definitions
   75 00002000 4C000000 
                       CLK_BASE
                               EQU              0x4C000000  ; Clock Base Addres
                                                            s
   76 00002000 00000000 
                       LOCKTIME_OFS
                               EQU              0x00        ; LOCKTIME Offset
   77 00002000 00000004 
                       MPLLCON_OFS
                               EQU              0x04        ; MPLLCON Offset
   78 00002000 00000008 
                       UPLLCON_OFS
                               EQU              0X08        ; UPLLCON Offset
   79 00002000 0000000C 
                       CLKCON_OFS
                               EQU              0x0C        ; CLKCON Offset
   80 00002000 00000010 
                       CLKSLOW_OFS
                               EQU              0x10        ; CLKSLOW Offset
   81 00002000 00000014 
                       CLKDIVN_OFS
                               EQU              0X14        ; CLDKIVN Offset
   82 00002000 00000018 
                       CAMDIVN_OFS
                               EQU              0X18        ; CAMDIVN Offset
   83 00002000         
   84 00002000         
   85 00002000         
   86 00002000         ;// <e> Clock Management
   87 00002000         ;//   <h> MPLL Settings
   88 00002000         ;//   <i> Mpll = (m * Fin) / (p * 2^s)
   89 00002000         ;//     <o1.12..19> MDIV: Main divider <0x0-0xFF>
   90 00002000         ;//                 <i> m = MDIV + 8
   91 00002000         ;//     <o1.4..9>   PDIV: Pre-divider  <0x0-0x3F>
   92 00002000         ;//                 <i> p = PDIV + 2
   93 00002000         ;//     <o1.0..1>   SDIV: Post Divider <0x0-0x03>
   94 00002000         ;//                 <i> s = SDIV 
   95 00002000         ;//   </h>



ARM Macro Assembler    Page 4 


   96 00002000         ;//   <h> UPLL Settings
   97 00002000         ;//   <i> Upll = ( m * Fin) / (p * 2^s),Uclk must be 48M
                       HZ to USB device 
   98 00002000         ;//     <o2.12..19> MDIV: Main divider <0x1-0xF8>
   99 00002000         ;//                 <i> m = MDIV + 8,if Fin=12MHZ MDIV c
                       ould be 0x38   
  100 00002000         ;//     <o2.4..9>   PDIV: Pre-divider  <0x1-0x3E>
  101 00002000         ;//                 <i> p = PDIV + 2,if Fin=12MHZ PDIV c
                       ould be 0x2
  102 00002000         ;//     <o2.0..1>   SDIV: Post Divider <0x0-0x03>
  103 00002000         ;//                 <i> s = SDIV ,if Fin=12MHZ SDIV coul
                       d be 0x2
  104 00002000         ;//   </h>
  105 00002000         ;//   <h>LOCK TIME 
  106 00002000         ;//      <o5.0..11>  LTIME CNT: MPLL Lock Time Count  <0
                       x0-0xFFF>
  107 00002000         ;//      <o5.12..23>  LTIME CNT: UPLL Lock Time Count  <
                       0x0-0xFFF>
  108 00002000         ;//   </h>
  109 00002000         ;//   <h> Master Clock
  110 00002000         ;//   <i> PLL Clock:  FCLK = FMPLL
  111 00002000         ;//   <i> Slow Clock: FCLK = Fin / (2 * SLOW_VAL), SLOW_
                       VAL > 0
  112 00002000         ;//   <i> Slow Clock: FCLK = Fin, SLOW_VAL = 0
  113 00002000         ;//     <o4.7>      UCLK_ON: UCLK ON
  114 00002000         ;//                 <i> 0: UCLK ON(UPLL is also turned o
                       n) 1: UCLK OFF (UPLL is also turned off)   
  115 00002000         ;//     <o4.5>      MPLL_OFF: Turn off PLL
  116 00002000         ;//                 <i> 0: Turn on PLL.After PLL stabili
                       zation time (minimum 300us), SLOW_BIT can be cleared to 
                       0. 1: Turn off PLL. PLL is turned off only when SLOW_BIT
                        is 1.
  117 00002000         ;//     <o4.4>      SLOW_BIT: Slow Clock
  118 00002000         ;//     <o4.0..2>   SLOW_VAL: Slow Clock divider    <0x0
                       -0x7>
  119 00002000         ;//   </h>
  120 00002000         ;//   <h> CLOCK DIVIDER CONTROL
  121 00002000         ;//     <o6.1>   HDIVN                            
  122 00002000         ;//                  <i> 0: HCLK = FCLK/1, 01 : HCLK = F
                       CLK/2
  123 00002000         ;//     <o6.0>      PDIVN
  124 00002000         ;//                  <i> 0: PCLK has the clock same as t
                       he HCLK/1,1: PCLK has the clock same as the HCLK/2
  125 00002000         ;//    </h>
  126 00002000         ;//  <h> Clock Generation
  127 00002000         ;//     <o3.18>     SPI          <0=> Disable  <1=> Enab
                       le
  128 00002000         ;//     <o3.17>     IIS          <0=> Disable  <1=> Enab
                       le
  129 00002000         ;//     <o3.16>     IIC          <0=> Disable  <1=> Enab
                       le
  130 00002000         ;//     <o3.15>     ADC          <0=> Disable  <1=> Enab
                       le
  131 00002000         ;//     <o3.14>     RTC          <0=> Disable  <1=> Enab
                       le
  132 00002000         ;//     <o3.13>     GPIO         <0=> Disable  <1=> Enab
                       le
  133 00002000         ;//     <o3.12>     UART2        <0=> Disable  <1=> Enab
                       le



ARM Macro Assembler    Page 5 


  134 00002000         ;//     <o3.11>     UART1        <0=> Disable  <1=> Enab
                       le
  135 00002000         ;//     <o3.10>     UART0        <0=> Disable  <1=> Enab
                       le
  136 00002000         ;//     <o3.9>      SDI          <0=> Disable  <1=> Enab
                       le
  137 00002000         ;//     <o3.8>      PWMTIMER     <0=> Disable  <1=> Enab
                       le
  138 00002000         ;//     <o3.7>      USB device   <0=> Disable  <1=> Enab
                       le
  139 00002000         ;//     <o3.6>      USB host     <0=> Disable  <1=> Enab
                       le
  140 00002000         ;//     <o3.5>      LCDC         <0=> Disable  <1=> Enab
                       le
  141 00002000         ;//     <o3.4>      NAND FLASH Controller       <0=> Dis
                       able  <1=> Enable
  142 00002000         ;//     <o3.3>      POWER-OFF    <0=> Disable  <1=> Enab
                       le
  143 00002000         ;//     <o3.2>      IDLE BIT     <0=> Disable  <1=> Enab
                       le
  144 00002000         ;//     <O3.0>      SM_BIT       <0=> Disable  <1=> Enab
                       le
  145 00002000         ;//   </h>
  146 00002000         ;// </e>
  147 00002000 00000001 
                       CLK_SETUP
                               EQU              1
  148 00002000 0005C042 
                       MPLLCON_Val
                               EQU              0x0005C042
  149 00002000 00028080 
                       UPLLCON_Val
                               EQU              0x00028080
  150 00002000 FFFFFFF0 
                       CLKCON_Val
                               EQU              0xFFFFFFF0
  151 00002000 00000004 
                       CLKSLOW_Val
                               EQU              0x00000004
  152 00002000 00FFFFFF 
                       LOCKTIME_Val
                               EQU              0x00FFFFFF
  153 00002000 00000003 
                       CLKDIVN_Val
                               EQU              0X00000003
  154 00002000         
  155 00002000         
  156 00002000         
  157 00002000         ;Interrupt  definitions
  158 00002000 4A000014 
                       INTOFFSET
                               EQU              0X4A000014  ;Address of Interru
                                                            pt offset Register
  159 00002000         
  160 00002000         ;//<e> Interrupt Vector Table
  161 00002000         ;//  <o1.0..31> Interrupt Vector address     <0x20-0x3ff
                       fff78>
  162 00002000         ;//            <i> You could define Interuupt Vctor Tabl
                       e address.  



ARM Macro Assembler    Page 6 


  163 00002000         ;//            <i> The Interrupt Vector Table address mu
                       st be word aligned adress. 
  164 00002000         ;//</e>  
  165 00002000 00000001 
                       IntVT_SETUP
                               EQU              1
  166 00002000 33FFFF20 
                       IntVTAddress
                               EQU              0x33FFFF20
  167 00002000         
  168 00002000         ; Watchdog Timer definitions
  169 00002000 53000000 
                       WT_BASE EQU              0x53000000  ; WT Base Address
  170 00002000 00000000 
                       WTCON_OFS
                               EQU              0x00        ; WTCON Offset
  171 00002000 00000004 
                       WTDAT_OFS
                               EQU              0x04        ; WTDAT Offset
  172 00002000 00000008 
                       WTCNT_OFS
                               EQU              0x08        ; WTCNT Offset
  173 00002000         
  174 00002000         ;// <e> Watchdog Timer
  175 00002000         ;//   <o1.5>      Watchdog Timer Enable/Disable
  176 00002000         ;//   <o1.0>      Reset Enable/Disable
  177 00002000         ;//   <o1.2>      Interrupt Enable/Disable
  178 00002000         ;//   <o1.3..4>   Clock Select  
  179 00002000         ;//               <0=> 1/16  <1=> 1/32  <2=> 1/64  <3=> 
                       1/128
  180 00002000         ;//               <i> Clock Division Factor
  181 00002000         ;//   <o1.8..15>  Prescaler Value <0x0-0xFF>
  182 00002000         ;//   <o2.0..15>  Time-out Value  <0x0-0xFFFF>
  183 00002000         ;// </e>
  184 00002000 00000001 
                       WT_SETUP
                               EQU              1
  185 00002000 00000000 
                       WTCON_Val
                               EQU              0x00000000
  186 00002000 FFFF8000 
                       WTDAT_Val
                               EQU              0xFFFF8000
  187 00002000         
  188 00002000         
  189 00002000         ; Memory Controller definitions
  190 00002000 48000000 
                       MC_BASE EQU              0x48000000  ; Memory Controller
                                                             Base Address
  191 00002000         
  192 00002000         ;// <e> Memory Controller
  193 00002000 00000001 
                       MC_SETUP
                               EQU              1
  194 00002000         
  195 00002000         ;//   <h> Bank 0
  196 00002000         ;//     <o0.0..1>   PMC: Page Mode Configuration
  197 00002000         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data



ARM Macro Assembler    Page 7 


  198 00002000         ;//     <o0.2..3>   Tpac: Page Mode Access Cycle
  199 00002000         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  200 00002000         ;//     <o0.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  201 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  202 00002000         ;//     <o0.6..7>   Toch: Chip Select Hold on nOE
  203 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  204 00002000         ;//     <o0.8..10>  Tacc: Access Cycle
  205 00002000         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  206 00002000         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  207 00002000         ;//     <o0.11..12> Tcos: Chip Select Set-up nOE
  208 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  209 00002000         ;//     <o0.13..14> Tacs: Address Set-up before nGCSn
  210 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  211 00002000         ;//   </h>
  212 00002000         ;//
  213 00002000         ;//   <h> Bank 1
  214 00002000         ;//     <o8.4..5>   DW: Data Bus Width
  215 00002000         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  216 00002000         ;//     <o8.6>      WS: WAIT Status
  217 00002000         ;//                 <0=> WAIT Disable
  218 00002000         ;//                 <1=> WAIT Enable
  219 00002000         ;//     <o8.7>      ST: SRAM Type
  220 00002000         ;//                 <0=> Not using UB/LB
  221 00002000         ;//                 <1=> Using UB/LB
  222 00002000         ;//     <o1.0..1>   PMC: Page Mode Configuration
  223 00002000         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  224 00002000         ;//     <o1.2..3>   Tpac: Page Mode Access Cycle
  225 00002000         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  226 00002000         ;//     <o1.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  227 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  228 00002000         ;//     <o1.6..7>   Toch: Chip Select Hold on nOE
  229 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  230 00002000         ;//     <o1.8..10>  Tacc: Access Cycle
  231 00002000         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  232 00002000         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  233 00002000         ;//     <o1.11..12> Tcos: Chip Select Set-up nOE
  234 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  235 00002000         ;//     <o1.13..14> Tacs: Address Set-up before nGCSn
  236 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  237 00002000         ;//   </h>
  238 00002000         ;//



ARM Macro Assembler    Page 8 


  239 00002000         ;//   <h> Bank 2
  240 00002000         ;//     <o8.8..9>   DW: Data Bus Width
  241 00002000         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  242 00002000         ;//     <o8.10>     WS: WAIT Status
  243 00002000         ;//                 <0=> WAIT Disable
  244 00002000         ;//                 <1=> WAIT Enable
  245 00002000         ;//     <o8.11>     ST: SRAM Type
  246 00002000         ;//                 <0=> Not using UB/LB
  247 00002000         ;//                 <1=> Using UB/LB
  248 00002000         ;//     <o2.0..1>   PMC: Page Mode Configuration
  249 00002000         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  250 00002000         ;//     <o2.2..3>   Tpac: Page Mode Access Cycle
  251 00002000         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  252 00002000         ;//     <o2.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  253 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  254 00002000         ;//     <o2.6..7>   Toch: Chip Select Hold on nOE
  255 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  256 00002000         ;//     <o2.8..10>  Tacc: Access Cycle
  257 00002000         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  258 00002000         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  259 00002000         ;//     <o2.11..12> Tcos: Chip Select Set-up nOE
  260 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  261 00002000         ;//     <o2.13..14> Tacs: Address Set-up before nGCSn
  262 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  263 00002000         ;//   </h>
  264 00002000         ;//
  265 00002000         ;//   <h> Bank 3
  266 00002000         ;//     <o8.12..13> DW: Data Bus Width
  267 00002000         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  268 00002000         ;//     <o8.14>     WS: WAIT Status
  269 00002000         ;//                 <0=> WAIT Disable
  270 00002000         ;//                 <1=> WAIT Enable
  271 00002000         ;//     <o8.15>     ST: SRAM Type
  272 00002000         ;//                 <0=> Not using UB/LB
  273 00002000         ;//                 <1=> Using UB/LB
  274 00002000         ;//     <o3.0..1>   PMC: Page Mode Configuration
  275 00002000         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  276 00002000         ;//     <o3.2..3>   Tpac: Page Mode Access Cycle
  277 00002000         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  278 00002000         ;//     <o3.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  279 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  280 00002000         ;//     <o3.6..7>   Toch: Chip Select Hold on nOE
  281 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks



ARM Macro Assembler    Page 9 


  282 00002000         ;//     <o3.8..10>  Tacc: Access Cycle
  283 00002000         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  284 00002000         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  285 00002000         ;//     <o3.11..12> Tcos: Chip Select Set-up nOE
  286 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  287 00002000         ;//     <o3.13..14> Tacs: Address Set-up before nGCSn
  288 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  289 00002000         ;//   </h>
  290 00002000         ;//
  291 00002000         ;//   <h> Bank 4
  292 00002000         ;//     <o8.16..17> DW: Data Bus Width
  293 00002000         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  294 00002000         ;//     <o8.18>     WS: WAIT Status
  295 00002000         ;//                 <0=> WAIT Disable
  296 00002000         ;//                 <1=> WAIT Enable
  297 00002000         ;//     <o8.19>     ST: SRAM Type
  298 00002000         ;//                 <0=> Not using UB/LB
  299 00002000         ;//                 <1=> Using UB/LB
  300 00002000         ;//     <o4.0..1>   PMC: Page Mode Configuration
  301 00002000         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  302 00002000         ;//     <o4.2..3>   Tpac: Page Mode Access Cycle
  303 00002000         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  304 00002000         ;//     <o4.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  305 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  306 00002000         ;//     <o4.6..7>   Toch: Chip Select Hold on nOE
  307 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  308 00002000         ;//     <o4.8..10>  Tacc: Access Cycle
  309 00002000         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  310 00002000         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  311 00002000         ;//     <o4.11..12> Tcos: Chip Select Set-up nOE
  312 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  313 00002000         ;//     <o4.13..14> Tacs: Address Set-up before nGCSn
  314 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  315 00002000         ;//   </h>
  316 00002000         ;//
  317 00002000         ;//   <h> Bank 5
  318 00002000         ;//     <o8.20..21> DW: Data Bus Width
  319 00002000         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  320 00002000         ;//     <o8.22>     WS: WAIT Status
  321 00002000         ;//                 <0=> WAIT Disable
  322 00002000         ;//                 <1=> WAIT Enable
  323 00002000         ;//     <o8.23>     ST: SRAM Type
  324 00002000         ;//                 <0=> Not using UB/LB
  325 00002000         ;//                 <1=> Using UB/LB



ARM Macro Assembler    Page 10 


  326 00002000         ;//     <o5.0..1>   PMC: Page Mode Configuration
  327 00002000         ;//                 <0=> 1 Data  <1=> 4 Data  <2=> 8 Dat
                       a  <3=> 16 Data
  328 00002000         ;//     <o5.2..3>   Tpac: Page Mode Access Cycle
  329 00002000         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  330 00002000         ;//     <o5.4..5>   Tcah: Address Holding Time after nGC
                       Sn
  331 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  332 00002000         ;//     <o5.6..7>   Toch: Chip Select Hold on nOE
  333 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  334 00002000         ;//     <o5.8..10>  Tacc: Access Cycle
  335 00002000         ;//                 <0=> 1 clk   <1=> 2 clks  <2=> 3 clk
                       s  <3=> 4 clks
  336 00002000         ;//                 <4=> 6 clk   <5=> 8 clks  <6=> 10 cl
                       ks <7=> 14 clks
  337 00002000         ;//     <o5.11..12> Tcos: Chip Select Set-up nOE
  338 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  339 00002000         ;//     <o5.13..14> Tacs: Address Set-up before nGCSn
  340 00002000         ;//                 <0=> 0 clk   <1=> 1 clk   <2=> 2 clk
                       s  <3=> 4 clks
  341 00002000         ;//   </h>
  342 00002000         ;//
  343 00002000         ;//   <h> Bank 6
  344 00002000         ;//     <o10.0..2>  BK76MAP: Bank 6/7 Memory Map
  345 00002000         ;//                 <0=> 32M  <1=> 64M <2=> 128M <4=> 2M
                          <5=> 4M   <6=> 8M   <7=> 16M
  346 00002000         ;//     <o8.24..25> DW: Data Bus Width
  347 00002000         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  348 00002000         ;//     <o8.26>     WS: WAIT Status
  349 00002000         ;//                 <0=> WAIT Disable
  350 00002000         ;//                 <1=> WAIT Enable
  351 00002000         ;//     <o8.27>     ST: SRAM Type
  352 00002000         ;//                 <0=> Not using UB/LB
  353 00002000         ;//                 <1=> Using UB/LB
  354 00002000         ;//     <o6.15..16> MT: Memory Type
  355 00002000         ;//                 <0=> ROM or SRAM
  356 00002000         ;//                 <3=> SDRAM
  357 00002000         ;//     <h> ROM or SRAM
  358 00002000         ;//       <o6.0..1>   PMC: Page Mode Configuration
  359 00002000         ;//                   <0=> 1 Data  <1=> 4 Data  <2=> 8 D
                       ata  <3=> 16 Data
  360 00002000         ;//       <o6.2..3>   Tpac: Page Mode Access Cycle
  361 00002000         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  362 00002000         ;//       <o6.4..5>   Tcah: Address Holding Time after n
                       GCSn
  363 00002000         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  364 00002000         ;//       <o6.6..7>   Toch: Chip Select Hold on nOE
  365 00002000         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  366 00002000         ;//       <o6.8..10>  Tacc: Access Cycle
  367 00002000         ;//                   <0=> 1 clk   <1=> 2 clks  <2=> 3 c
                       lks  <3=> 4 clks



ARM Macro Assembler    Page 11 


  368 00002000         ;//                   <4=> 6 clk   <5=> 8 clks  <6=> 10 
                       clks <7=> 14 clks
  369 00002000         ;//       <o6.11..12> Tcos: Chip Select Set-up nOE
  370 00002000         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  371 00002000         ;//       <o6.13..14> Tacs: Address Set-up before nGCSn
  372 00002000         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  373 00002000         ;//     </h>
  374 00002000         ;//     <h> SDRAM
  375 00002000         ;//       <o6.0..1>   SCAN: Columnn Address Number
  376 00002000         ;//                   <0=> 8-bit   <1=> 9-bit   <2=> 10-
                       bit  <3=> Rsrvd
  377 00002000         ;//       <o6.2..3>   Trcd: RAS to CAS Delay
  378 00002000         ;//                   <0=> 2 clks  <1=> 3 clks  <2=> 4 c
                       lks  <3=> Rsrvd
  379 00002000         ;//       <o10.4>     SCKEEN: SCLK Selection (Bank 6/7)
  380 00002000         ;//                   <0=> Normal
  381 00002000         ;//                   <1=> Reduced Power   
  382 00002000         ;//       <o10.5>     SCLKEN: SDRAM power down mode (Ban
                       k 6/7)
  383 00002000         ;//                   <0=> DISABLE
  384 00002000         ;//                   <1=> ENABLE 
  385 00002000         ;//       <o10.7>     BURST_EN: ARM core burst operation
                        (Bank 6/7)
  386 00002000         ;//                   <0=> DISABLE
  387 00002000         ;//                   <1=> ENABLE 
  388 00002000         ;//       <o11.0..2>  BL: Burst Length
  389 00002000         ;//                   <0=> 1
  390 00002000         ;//       <o11.3>     BT: Burst Type
  391 00002000         ;//                   <0=> Sequential
  392 00002000         ;//       <o11.4..6>  CL: CAS Latency
  393 00002000         ;//                   <0=> 1 clk   <1=> 2 clks  <3=> 3 c
                       lks
  394 00002000         ;//       <o11.7..8>  TM: Test Mode
  395 00002000         ;//                   <0=> Mode Register Set
  396 00002000         ;//       <o11.9>     WBL: Write Burst Length
  397 00002000         ;//                   <0=> 0
  398 00002000         ;//     </h>
  399 00002000         ;//   </h>
  400 00002000         ;//
  401 00002000         ;//   <h> Bank 7
  402 00002000         ;//     <o10.0..2>  BK76MAP: Bank 6/7 Memory Map
  403 00002000         ;//                 <0=> 32M  <1=> 64M <2=> 128M <4=> 2M
                          <5=> 4M   <6=> 8M   <7=> 16M
  404 00002000         ;//     <o8.28..29> DW: Data Bus Width
  405 00002000         ;//                 <0=> 8-bit   <1=> 16-bit  <2=> 32-bi
                       t  <3=> Rsrvd
  406 00002000         ;//     <o8.30>     WS: WAIT Status
  407 00002000         ;//                 <0=> WAIT Disable
  408 00002000         ;//                 <1=> WAIT Enable
  409 00002000         ;//     <o8.31>     ST: SRAM Type
  410 00002000         ;//                 <0=> Not using UB/LB
  411 00002000         ;//                 <1=> Using UB/LB
  412 00002000         ;//     <o7.15..16> MT: Memory Type
  413 00002000         ;//                 <0=> ROM or SRAM
  414 00002000         ;//                 <3=> SDRAM
  415 00002000         ;//     <h> ROM or SRAM
  416 00002000         ;//       <o7.0..1>   PMC: Page Mode Configuration



ARM Macro Assembler    Page 12 


  417 00002000         ;//                   <0=> 1 Data  <1=> 4 Data  <2=> 8 D
                       ata  <3=> 16 Data
  418 00002000         ;//       <o7.2..3>   Tpac: Page Mode Access Cycle
  419 00002000         ;//                 <0=> 2 clks  <1=> 3 clks  <2=> 4 clk
                       s  <3=> 6 clks
  420 00002000         ;//       <o7.4..5>   Tcah: Address Holding Time after n
                       GCSn
  421 00002000         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  422 00002000         ;//       <o7.6..7>   Toch: Chip Select Hold on nOE
  423 00002000         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  424 00002000         ;//       <o7.8..10>  Tacc: Access Cycle
  425 00002000         ;//                   <0=> 1 clk   <1=> 2 clks  <2=> 3 c
                       lks  <3=> 4 clks
  426 00002000         ;//                   <4=> 6 clk   <5=> 8 clks  <6=> 10 
                       clks <7=> 14 clks
  427 00002000         ;//       <o7.11..12> Tcos: Chip Select Set-up nOE
  428 00002000         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  429 00002000         ;//       <o7.13..14> Tacs: Address Set-up before nGCSn
  430 00002000         ;//                   <0=> 0 clk   <1=> 1 clk   <2=> 2 c
                       lks  <3=> 4 clks
  431 00002000         ;//     </h>
  432 00002000         ;//     <h> SDRAM
  433 00002000         ;//       <o7.0..1>   SCAN: Columnn Address Number
  434 00002000         ;//                   <0=> 8-bit   <1=> 9-bit   <2=> 10-
                       bit  <3=> Rsrvd
  435 00002000         ;//       <o7.2..3>   Trcd: RAS to CAS Delay
  436 00002000         ;//                   <0=> 2 clks  <1=> 3 clks  <2=> 4 c
                       lks  <3=> Rsrvd
  437 00002000         ;//       <o10.4>     SCLKEN: SCLK Selection (Bank 6/7)
  438 00002000         ;//                   <0=> Normal
  439 00002000         ;//                   <1=> Reduced Power 
  440 00002000         ;//       <o10.5>     SCLKEN: SDRAM power down mode (Ban
                       k 6/7)
  441 00002000         ;//                   <0=> DISABLE
  442 00002000         ;//                   <1=> ENABLE 
  443 00002000         ;//       <o10.7>     BURST_EN: ARM core burst operation
                        (Bank 6/7)
  444 00002000         ;//                   <0=> DISABLE
  445 00002000         ;//                   <1=> ENABLE 
  446 00002000         ;//       <o12.0..2>  BL: Burst Length
  447 00002000         ;//                   <0=> 1
  448 00002000         ;//       <o12.3>     BT: Burst Type
  449 00002000         ;//                   <0=> Sequential
  450 00002000         ;//       <o12.4..6>  CL: CAS Latency
  451 00002000         ;//                   <0=> 1 clk   <1=> 2 clks  <3=> 3 c
                       lks
  452 00002000         ;//       <o12.7..8>  TM: Test Mode
  453 00002000         ;//                   <0=> Mode Register Set
  454 00002000         ;//       <o12.9>     WBL: Write Burst Length
  455 00002000         ;//                   <0=> 0
  456 00002000         ;//     </h>
  457 00002000         ;//   </h>
  458 00002000         ;//
  459 00002000         ;//   <h> Refresh
  460 00002000         ;//     <o9.23>     REFEN: SDRAM Refresh
  461 00002000         ;//                 <0=> Disable <1=> Enable



ARM Macro Assembler    Page 13 


  462 00002000         ;//     <o9.22>     TREFMD: SDRAM Refresh Mode
  463 00002000         ;//                 <0=> CBR/Auto Refresh
  464 00002000         ;//                 <1=> Self Refresh
  465 00002000         ;//     <o9.20..21> Trp: SDRAM RAS Pre-charge Time
  466 00002000         ;//                 <0=> 2 clks 
  467 00002000         ;//                 <1=> 3 clks 
  468 00002000         ;//                 <2=> 4 clks 
  469 00002000         ;//                 <3=> Rsrvd 
  470 00002000         ;//     <o9.18..19> Tsrc: SDRAM Semi Row cycle time
  471 00002000         ;//                <i> SDRAM Row cycle time: Trc=Tsrc+Tr
                       p
  472 00002000         ;//                 <0=> 4 clks  <1=> 5 clks  <2=> 6 clk
                       s  <3=> 7 clks
  473 00002000         ;//     <o9.0..10>  Refresh Counter <0x0-0x07FF>
  474 00002000         ;//                 <i> Refresh Period = (2^11 - Refresh
                        Count + 1) / HCLK
  475 00002000         ;//   </h>
  476 00002000 00000700 
                       BANKCON0_Val
                               EQU              0x00000700
  477 00002000 00000700 
                       BANKCON1_Val
                               EQU              0x00000700
  478 00002000 00000700 
                       BANKCON2_Val
                               EQU              0x00000700
  479 00002000 00000700 
                       BANKCON3_Val
                               EQU              0x00000700
  480 00002000 00000700 
                       BANKCON4_Val
                               EQU              0x00000700
  481 00002000 00000700 
                       BANKCON5_Val
                               EQU              0x00000700
  482 00002000 00018005 
                       BANKCON6_Val
                               EQU              0x00018005
  483 00002000 00018005 
                       BANKCON7_Val
                               EQU              0x00018005
  484 00002000 22111120 
                       BWSCON_Val
                               EQU              0x22111120
  485 00002000 008E0459 
                       REFRESH_Val
                               EQU              0x008E0459
  486 00002000 000000B2 
                       BANKSIZE_Val
                               EQU              0x000000B2
  487 00002000 00000030 
                       MRSRB6_Val
                               EQU              0x00000030
  488 00002000 00000030 
                       MRSRB7_Val
                               EQU              0x00000030
  489 00002000         
  490 00002000         ;// </e> End of MC
  491 00002000         



ARM Macro Assembler    Page 14 


  492 00002000         
  493 00002000         
  494 00002000         ; I/O Ports definitions
  495 00002000 56000000 
                       PIO_BASE
                               EQU              0x56000000  ; PIO Base Address
  496 00002000 00000000 
                       PCONA_OFS
                               EQU              0x00        ; PCONA Offset
  497 00002000 00000010 
                       PCONB_OFS
                               EQU              0x10        ; PCONB Offset
  498 00002000 00000020 
                       PCONC_OFS
                               EQU              0x20        ; PCONC Offset
  499 00002000 00000030 
                       PCOND_OFS
                               EQU              0x30        ; PCOND Offset
  500 00002000 00000040 
                       PCONE_OFS
                               EQU              0x40        ; PCONE Offset
  501 00002000 00000050 
                       PCONF_OFS
                               EQU              0x50        ; PCONF Offset
  502 00002000 00000060 
                       PCONG_OFS
                               EQU              0x60        ; PCONG Offset
  503 00002000 00000070 
                       PCONH_OFS
                               EQU              0x70        ; PCONH Offset
  504 00002000         ;PCONJ_OFS       EQU     0xD0            ; PCONJ Offset
  505 00002000 00000018 
                       PUPB_OFS
                               EQU              0x18        ; PUPB Offset
  506 00002000 00000028 
                       PUPC_OFS
                               EQU              0x28        ; PUPC Offset
  507 00002000 00000038 
                       PUPD_OFS
                               EQU              0x38        ; PUPD Offset
  508 00002000 00000048 
                       PUPE_OFS
                               EQU              0x48        ; PUPE Offset
  509 00002000 00000058 
                       PUPF_OFS
                               EQU              0x58        ; PUPF Offset
  510 00002000 00000068 
                       PUPG_OFS
                               EQU              0x68        ; PUPG Offset
  511 00002000 00000078 
                       PUPH_OFS
                               EQU              0x78        ; PUPH Offset
  512 00002000 000000D8 
                       PUPJ_OFS
                               EQU              0xD8        ; PUPJ Offset
  513 00002000 00000004 
                       PDAA_OFS
                               EQU              0x04
  514 00002000 00000014 



ARM Macro Assembler    Page 15 


                       PDAB_OFS
                               EQU              0x14
  515 00002000 00000024 
                       PDAC_OFS
                               EQU              0x24
  516 00002000 00000034 
                       PDAD_OFS
                               EQU              0x34
  517 00002000 00000044 
                       PDAE_OFS
                               EQU              0x44
  518 00002000 00000054 
                       PDAF_OFS
                               EQU              0x54
  519 00002000 00000064 
                       PDAG_OFS
                               EQU              0x64
  520 00002000 00000074 
                       PDAH_OFS
                               EQU              0x74
  521 00002000         
  522 00002000         
  523 00002000         
  524 00002000         
  525 00002000         ;// <e> I/O Configuration
  526 00002000 00000000 
                       PIO_SETUP
                               EQU              0
  527 00002000         
  528 00002000         ;//   <e> Port A
  529 00002000         ;//     <o1.0>      PA0  <0=> Output   <1=> ADDR0
  530 00002000         ;//     <o1.1>      PA1  <0=> Output   <1=> ADDR16
  531 00002000         ;//     <o1.2>      PA2  <0=> Output   <1=> ADDR17
  532 00002000         ;//     <o1.3>      PA3  <0=> Output   <1=> ADDR18
  533 00002000         ;//     <o1.4>      PA4  <0=> Output   <1=> ADDR19
  534 00002000         ;//     <o1.5>      PA5  <0=> Output   <1=> ADDR20
  535 00002000         ;//     <o1.6>      PA6  <0=> Output   <1=> ADDR21
  536 00002000         ;//     <o1.7>      PA7  <0=> Output   <1=> ADDR22
  537 00002000         ;//     <o1.8>      PA8  <0=> Output   <1=> ADDR23
  538 00002000         ;//     <o1.9>      PA9  <0=> Output   <1=> ADDR24
  539 00002000         ;//     <o1.10>      PA0  <0=> Output   <1=> ADDR25
  540 00002000         ;//     <o1.11>      PA1  <0=> Output   <1=> ADDR26
  541 00002000         ;//     <o1.12>      PA2  <0=> Output   <1=> nGCS[1]
  542 00002000         ;//     <o1.13>      PA3  <0=> Output   <1=> nGCS[2]
  543 00002000         ;//     <o1.14>      PA4  <0=> Output   <1=> nGCS[3]
  544 00002000         ;//     <o1.15>      PA5  <0=> Output   <1=> nGCS[4]
  545 00002000         ;//     <o1.16>      PA6  <0=> Output   <1=> nGCS[5]
  546 00002000         ;//     <o1.17>      PA7  <0=> Output   <1=> CLE
  547 00002000         ;//     <o1.18>      PA8  <0=> Output   <1=> ALE
  548 00002000         ;//     <o1.19>      PA9  <0=> Output   <1=> nFWE
  549 00002000         ;//     <o1.20>      PA0  <0=> Output   <1=> nFRE
  550 00002000         ;//     <o1.21>      PA1  <0=> Output   <1=> nRSTOUT
  551 00002000         ;//     <o1.22>      PA2  <0=> Output   <1=> nFCE
  552 00002000         ;//   </e>
  553 00002000 00000001 
                       PIOA_SETUP
                               EQU              1
  554 00002000 005EF7FF 
                       PCONA_Val



ARM Macro Assembler    Page 16 


                               EQU              0x5ef7ff
  555 00002000         
  556 00002000         ;//   <e> Port B
  557 00002000         ;//     <o1.0..1>        PB0  <0=> Input   <1=> Output  
                       <2=> TOUT0    <3=> Reserved 
  558 00002000         ;//     <o1.2..3>        PB1  <0=> Input   <1=> Output  
                       <2=> TOUT1    <3=> Reserved 
  559 00002000         ;//     <o1.4..5>        PB2  <0=> Input   <1=> Output  
                       <2=> TOUT2    <3=> Reserved 
  560 00002000         ;//     <o1.6..7>        PB3  <0=> Input   <1=> Output  
                       <2=> TOUT3    <3=> Reserved 
  561 00002000         ;//     <o1.8..9>        PB4  <0=> Input   <1=> Output  
                       <2=> TCLK[0]  <3=> Reserved 
  562 00002000         ;//     <o1.10..11>      PB5  <0=> Input   <1=> Output  
                       <2=> nXBACK   <3=> Reserved 
  563 00002000         ;//     <o1.12..13>      PB6  <0=> Input   <1=> Output  
                       <2=> nXBREQ   <3=> Reserved 
  564 00002000         ;//     <o1.14..15>      PB7  <0=> Input   <1=> Output  
                       <2=> nXDACK1  <3=> Reserved 
  565 00002000         ;//     <o1.16..17>      PB8  <0=> Input   <1=> Output  
                       <2=> nXDREQ1  <3=> Reserved 
  566 00002000         ;//     <o1.18..19>      PB9  <0=> Input   <1=> Output  
                       <2=> nXDACK0  <3=> Reserved 
  567 00002000         ;//     <o1.20..21>      PB10 <0=> Input   <1=> Output  
                       <2=> nXDREQ0  <3=> Reserved 
  568 00002000         ;//     <h> Pull-up Resistors                           
                                    
  569 00002000         ;//       <o2.0>    PB0 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  570 00002000         ;//       <o2.1>    PB1 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  571 00002000         ;//       <o2.2>    PB2 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  572 00002000         ;//       <o2.3>    PB3 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  573 00002000         ;//       <o2.4>    PB4 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  574 00002000         ;//       <o2.5>    PB5 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  575 00002000         ;//       <o2.6>    PB6 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  576 00002000         ;//       <o2.7>    PB7 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  577 00002000         ;//       <o2.8>    PB8 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  578 00002000         ;//       <o2.9>    PB9 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  579 00002000         ;//       <o2.10>   PB10 Pull-up       <0=> Enabled  <1=
                       > Disabled   
  580 00002000         ;//     </h>                                            
                                    
  581 00002000         ;//   </e>
  582 00002000 00000001 
                       PIOB_SETUP
                               EQU              1
  583 00002000 00155559 
                       PCONB_Val
                               EQU              0x155559
  584 00002000 000007FF 



ARM Macro Assembler    Page 17 


                       PUPB_Val
                               EQU              0x7ff
  585 00002000         
  586 00002000         ;//   <e> Port C
  587 00002000         ;//     <o1.0..1>          PC0  <0=> Input    <1=> Outpu
                       t  <2=> LEND          <3=> Reserved 
  588 00002000         ;//     <o1.2..3>          PC1  <0=> Input    <1=> Outpu
                       t  <2=> VCLK          <3=> Reserved 
  589 00002000         ;//     <o1.4..5>          PC2  <0=> Input    <1=> Outpu
                       t  <2=> VLINE         <3=> Reserved 
  590 00002000         ;//     <o1.6..7>          PC3  <0=> Input    <1=> Outpu
                       t  <2=> VFRAME        <3=> Reserved 
  591 00002000         ;//     <o1.8..9>          PC4  <0=> Input    <1=> Outpu
                       t  <2=> VM            <3=> Reserved 
  592 00002000         ;//     <o1.10..11>        PC5  <0=> Input    <1=> Outpu
                       t  <2=> LCDVF2     <3=> Reserved 
  593 00002000         ;//     <o1.12..13>        PC6  <0=> Input    <1=> Outpu
                       t  <2=> LCDVF1    <3=> Reserved 
  594 00002000         ;//     <o1.14..15>        PC7  <0=> Input    <1=> Outpu
                       t  <2=> LCDVF0   <3=> Reserved 
  595 00002000         ;//     <o1.16..17>        PC8  <0=> Input    <1=> Outpu
                       t  <2=> VD[0]         <3=> Reserved 
  596 00002000         ;//     <o1.18..19>        PC9  <0=> Input    <1=> Outpu
                       t  <2=> VD[1]         <3=> Reserved 
  597 00002000         ;//     <o1.20..21>        PC10 <0=> Input    <1=> Outpu
                       t  <2=> VD[2]         <3=> Reserved 
  598 00002000         ;//     <o1.22..23>        PC11  <0=> Input   <1=> Outpu
                       t  <2=> VD[3]         <3=> Reserved 
  599 00002000         ;//     <o1.24..25>        PC12  <0=> Input   <1=> Outpu
                       t  <2=> VD[4]         <3=> Reserved 
  600 00002000         ;//     <o1.26..27>        PC13  <0=> Input   <1=> Outpu
                       t  <2=> VD[5]         <3=> Reserved 
  601 00002000         ;//     <o1.28..29>        PC14  <0=> Input   <1=> Outpu
                       t  <2=> VD[6]         <3=> Reserved 
  602 00002000         ;//     <o1.30..31>        PC15  <0=> Input   <1=> Outpu
                       t  <2=> VD[7]         <3=> Reserved 
  603 00002000         ;//     <h> Pull-up Resistors                           
                                    
  604 00002000         ;//       <o2.0>     PC0 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  605 00002000         ;//       <o2.1>     PC1 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  606 00002000         ;//       <o2.2>     PC2 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  607 00002000         ;//       <o2.3>     PC3 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  608 00002000         ;//       <o2.4>     PC4 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  609 00002000         ;//       <o2.5>     PC5 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  610 00002000         ;//       <o2.6>     PC6 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  611 00002000         ;//       <o2.7>     PC7 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  612 00002000         ;//       <o2.8>     PC8 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  613 00002000         ;//       <o2.9>     PC9 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  614 00002000         ;//       <o2.10>    PC10 Pull-up        <0=> Enabled  <



ARM Macro Assembler    Page 18 


                       1=> Disabled   
  615 00002000         ;//       <o2.11>    PC11 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  616 00002000         ;//       <o2.12>    PC12 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  617 00002000         ;//       <o2.13>    PC13 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  618 00002000         ;//       <o2.14>    PC14 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  619 00002000         ;//       <o2.15>    PC15 Pull-up        <0=> Enabled  <
                       1=> Disabled  
  620 00002000         ;//     </h>                                            
                                    
  621 00002000         ;//   </e>
  622 00002000 00000001 
                       PIOC_SETUP
                               EQU              1
  623 00002000 AAAA55AA 
                       PCONC_Val
                               EQU              0xaaaa55aa
  624 00002000 0000FFFF 
                       PUPC_Val
                               EQU              0xffff
  625 00002000 00000000 
                       PDAC_Val
                               EQU              0x0
  626 00002000         
  627 00002000         ;//   <e> Port D
  628 00002000         ;//     <o1.0..1>          PD0  <0=> Input    <1=> Outpu
                       t  <2=> VD[8]         <3=> Reserved 
  629 00002000         ;//     <o1.2..3>          PD1  <0=> Input    <1=> Outpu
                       t  <2=> VD[9]         <3=> Reserved 
  630 00002000         ;//     <o1.4..5>          PD2  <0=> Input    <1=> Outpu
                       t  <2=> VD[10]         <3=> Reserved 
  631 00002000         ;//     <o1.6..7>          PD3  <0=> Input    <1=> Outpu
                       t  <2=> VD[11]         <3=> Reserved 
  632 00002000         ;//     <o1.8..9>          PD4  <0=> Input    <1=> Outpu
                       t  <2=> VD[12]         <3=> Reserved 
  633 00002000         ;//     <o1.10..11>        PD5  <0=> Input    <1=> Outpu
                       t  <2=> VD[13]         <3=> Reserved 
  634 00002000         ;//     <o1.12..13>        PD6  <0=> Input    <1=> Outpu
                       t  <2=> VD[14]         <3=> Reserved 
  635 00002000         ;//     <o1.14..15>        PD7  <0=> Input    <1=> Outpu
                       t  <2=> VD[15]         <3=> Reserved 
  636 00002000         ;//     <o1.16..17>        PD8  <0=> Input    <1=> Outpu
                       t  <2=> VD[16]         <3=> Reserved  
  637 00002000         ;//     <o1.18..19>        PD9  <0=> Input    <1=> Outpu
                       t  <2=> VD[17]         <3=> Reserved 
  638 00002000         ;//     <o1.20..21>        PD10 <0=> Input    <1=> Outpu
                       t  <2=> VD[18]         <3=> Reserved 
  639 00002000         ;//     <o1.22..23>        PD11  <0=> Input   <1=> Outpu
                       t  <2=> VD[19]         <3=> Reserved 
  640 00002000         ;//     <o1.24..25>        PD12  <0=> Input   <1=> Outpu
                       t  <2=> VD[20]         <3=> Reserved 
  641 00002000         ;//     <o1.26..27>        PD13  <0=> Input   <1=> Outpu
                       t  <2=> VD[21]         <3=> Reserved 
  642 00002000         ;//     <o1.28..29>        PD14  <0=> Input   <1=> Outpu
                       t  <2=> VD[22]          <3=> nSS1
  643 00002000         ;//     <o1.30..31>        PD15  <0=> Input   <1=> Outpu



ARM Macro Assembler    Page 19 


                       t  <2=> VD[23]          <3=> nSS0 
  644 00002000         ;//     <h> Pull-up Resistors                           
                                    
  645 00002000         ;//       <o2.0>     PD0 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  646 00002000         ;//       <o2.1>     PD1 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  647 00002000         ;//       <o2.2>     PD2 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  648 00002000         ;//       <o2.3>     PD3 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  649 00002000         ;//       <o2.4>     PD4 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  650 00002000         ;//       <o2.5>     PD5 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  651 00002000         ;//       <o2.6>     PD6 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  652 00002000         ;//       <o2.7>     PD7 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  653 00002000         ;//       <o2.8>     PD8 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  654 00002000         ;//       <o2.9>     PD9 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  655 00002000         ;//       <o2.10>    PD10 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  656 00002000         ;//       <o2.11>    PD11 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  657 00002000         ;//       <o2.12>    PD12 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  658 00002000         ;//       <o2.13>    PD13 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  659 00002000         ;//       <o2.14>    PD14 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  660 00002000         ;//       <o2.15>    PD15 Pull-up        <0=> Enabled  <
                       1=> Disabled  
  661 00002000         ;//     </h>         
  662 00002000         ;//   </e>
  663 00002000 00000001 
                       PIOD_SETUP
                               EQU              1
  664 00002000 AAAAAAAA 
                       PCOND_Val
                               EQU              0xaaaaaaaa
  665 00002000 0000FFFF 
                       PUPD_Val
                               EQU              0xffff
  666 00002000         
  667 00002000         ;//   <e> Port E
  668 00002000         ;//     <o1.0..1>          PE0  <0=> Input    <1=> Outpu
                       t  <2=> I2SLRCK       <3=> Reserved 
  669 00002000         ;//     <o1.2..3>          PE1  <0=> Input    <1=> Outpu
                       t  <2=> I2SSCLK       <3=> Reserved  
  670 00002000         ;//     <o1.4..5>          PE2  <0=> Input    <1=> Outpu
                       t  <2=> CDCLK         <3=> Reserved 
  671 00002000         ;//     <o1.6..7>          PE3  <0=> Input    <1=> Outpu
                       t  <2=> I2SDI         <3=> nSS0 
  672 00002000         ;//     <o1.8..9>          PE4  <0=> Input    <1=> Outpu
                       t  <2=> I2SDO         <3=> I2SSDI 
  673 00002000         ;//     <o1.10..11>        PE5  <0=> Input    <1=> Outpu



ARM Macro Assembler    Page 20 


                       t  <2=> SDCLK         <3=> Reserved 
  674 00002000         ;//     <o1.12..13>        PE6  <0=> Input    <1=> Outpu
                       t  <2=> SDCMD         <3=> Reserved 
  675 00002000         ;//     <o1.14..15>        PE7  <0=> Input    <1=> Outpu
                       t  <2=> SDDAT0        <3=> Reserved 
  676 00002000         ;//     <o1.16..17>        PE8  <0=> Input    <1=> Outpu
                       t  <2=> SDDAT1        <3=> Reserved
  677 00002000         ;//     <o1.18..19>        PE9  <0=> Input    <1=> Outpu
                       t  <2=> SDDAT2        <3=> Reserved
  678 00002000         ;//     <o1.20..21>        PE10 <0=> Input    <1=> Outpu
                       t  <2=> SDDAT3        <3=> Reserved
  679 00002000         ;//     <o1.22..23>        PE11  <0=> Input   <1=> Outpu
                       t  <2=> SPIMISO0      <3=> Reserved 
  680 00002000         ;//     <o1.24..25>        PE12  <0=> Input   <1=> Outpu
                       t  <2=> SPIMOSI0      <3=> Reserved 
  681 00002000         ;//     <o1.26..27>        PE13  <0=> Input   <1=> Outpu
                       t  <2=> SPICLK0       <3=> Reserved 
  682 00002000         ;//     <o1.28..29>        PE14  <0=> Input   <1=> Outpu
                       t  <2=> IICSCL        <3=> Reserved
  683 00002000         ;//     <o1.30..31>        PE15  <0=> Input   <1=> Outpu
                       t  <2=> IICSDA        <3=> Reserved
  684 00002000         ;//     <h> Pull-up Resistors                           
                                                  
  685 00002000         ;//       <o2.0>     PE0 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  686 00002000         ;//       <o2.1>     PE1 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  687 00002000         ;//       <o2.2>     PE2 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  688 00002000         ;//       <o2.3>     PE3 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  689 00002000         ;//       <o2.4>     PE4 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  690 00002000         ;//       <o2.5>     PE5 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  691 00002000         ;//       <o2.6>     PE6 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  692 00002000         ;//       <o2.7>     PE7 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  693 00002000         ;//       <o2.8>     PE8 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  694 00002000         ;//       <o2.9>     PE9 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  695 00002000         ;//       <o2.10>    PE10 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  696 00002000         ;//       <o2.11>    PE11 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  697 00002000         ;//       <o2.12>    PE12 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  698 00002000         ;//       <o2.13>    PE13 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  699 00002000         ;//       <o2.14>    PE14 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  700 00002000         ;//       <o2.15>    PE15 Pull-up        <0=> Enabled  <
                       1=> Disabled  
  701 00002000         ;//     </h>         
  702 00002000         ;//   </e>
  703 00002000 00000001 
                       PIOE_SETUP



ARM Macro Assembler    Page 21 


                               EQU              1
  704 00002000 AAAAAAAA 
                       PCONE_Val
                               EQU              0xaaaaaaaa
  705 00002000 0000FFFF 
                       PUPE_Val
                               EQU              0xffff
  706 00002000         
  707 00002000         ;//   <e> Port F
  708 00002000         ;//     <o1.0..1>        PF0  <0=> Input   <1=> Output  
                       <2=> EINT[0]  <3=> Reserved 
  709 00002000         ;//     <o1.2..3>        PF1  <0=> Input   <1=> Output  
                       <2=> EINT[1]  <3=> Reserved 
  710 00002000         ;//     <o1.4..5>        PF2  <0=> Input   <1=> Output  
                       <2=> EINT[2]  <3=> Reserved 
  711 00002000         ;//     <o1.6..7>        PF3  <0=> Input   <1=> Output  
                       <2=> EINT[3]  <3=> Reserved 
  712 00002000         ;//     <o1.8..9>        PF4  <0=> Input   <1=> Output  
                       <2=> EINT[4]  <3=> Reserved 
  713 00002000         ;//     <o1.10..11>      PF5  <0=> Input   <1=> Output  
                       <2=> EINT[5]  <3=> Reserved 
  714 00002000         ;//     <o1.12..13>      PF6  <0=> Input   <1=> Output  
                       <2=> EINT[6]  <3=> Reserved 
  715 00002000         ;//     <o1.14..15>      PF7  <0=> Input   <1=> Output  
                       <2=> EINT[7]  <3=> Reserved 
  716 00002000         ;//     <h> Pull-up Resistors                           
                                    
  717 00002000         ;//       <o2.0>    PF0 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  718 00002000         ;//       <o2.1>    PF1 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  719 00002000         ;//       <o2.2>    PF2 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  720 00002000         ;//       <o2.3>    PF3 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  721 00002000         ;//       <o2.4>    PF4 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  722 00002000         ;//       <o2.5>    PF5 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  723 00002000         ;//       <o2.6>    PF6 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  724 00002000         ;//       <o2.7>    PF7 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  725 00002000         ;//     </h> 
  726 00002000         ;//   </e>
  727 00002000 00000001 
                       PIOF_SETUP
                               EQU              1
  728 00002000 000055AA 
                       PCONF_Val
                               EQU              0x55aa
  729 00002000 000000FF 
                       PUPF_Val
                               EQU              0xff
  730 00002000 0000000F 
                       PDAF_Val
                               EQU              0x0f
  731 00002000         
  732 00002000         ;//   <e> Port G



ARM Macro Assembler    Page 22 


  733 00002000         ;//     <o1.0..1>          PG0  <0=> Input    <1=> Outpu
                       t  <2=> EINT[8]   <3=> Reserved 
  734 00002000         ;//     <o1.2..3>          PG1  <0=> Input    <1=> Outpu
                       t  <2=> EINT[9]   <3=> Reserved 
  735 00002000         ;//     <o1.4..5>          PG2  <0=> Input    <1=> Outpu
                       t  <2=> EINT[10]   <3=> nSS0 
  736 00002000         ;//     <o1.6..7>          PG3  <0=> Input    <1=> Outpu
                       t  <2=> EINT[11]   <3=> nSS1 
  737 00002000         ;//     <o1.8..9>          PG4  <0=> Input    <1=> Outpu
                       t  <2=> EINT[12]   <3=> LCD_PWRDN 
  738 00002000         ;//     <o1.10..11>        PG5  <0=> Input    <1=> Outpu
                       t  <2=> EINT[13]   <3=> SPIMISO1 
  739 00002000         ;//     <o1.12..13>        PG6  <0=> Input    <1=> Outpu
                       t  <2=> EINT[14]   <3=> SPIMOSI1
  740 00002000         ;//     <o1.14..15>        PG7  <0=> Input    <1=> Outpu
                       t  <2=> EINT[15]   <3=> SPICLK1 
  741 00002000         ;//     <o1.16..17>        PG8  <0=> Input    <1=> Outpu
                       t  <2=> EINT[16]   <3=> Reserved 
  742 00002000         ;//     <o1.18..19>        PG9  <0=> Input    <1=> Outpu
                       t  <2=> EINT[17]   <3=> Reserved 
  743 00002000         ;//     <o1.20..21>        PG10 <0=> Input    <1=> Outpu
                       t  <2=> EINT[18]   <3=> Reserved 
  744 00002000         ;//     <o1.22..23>        PG11  <0=> Input   <1=> Outpu
                       t  <2=> EINT[19]   <3=> TCLK1
  745 00002000         ;//     <o1.24..25>        PG12  <0=> Input   <1=> Outpu
                       t  <2=> EINT[20]   <3=> XMON
  746 00002000         ;//     <o1.26..27>        PG13  <0=> Input   <1=> Outpu
                       t  <2=> EINT[21]   <3=> nXPON 
  747 00002000         ;//     <o1.28..29>        PG14  <0=> Input   <1=> Outpu
                       t  <2=> EINT[22]   <3=> YMON
  748 00002000         ;//     <o1.30..31>        PG15  <0=> Input   <1=> Outpu
                       t  <2=> EINT[23]   <3=> nYPON
  749 00002000         ;//     <h> Pull-up Resistors                           
                                    
  750 00002000         ;//       <o2.0>     PG0 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  751 00002000         ;//       <o2.1>     PG1 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  752 00002000         ;//       <o2.2>     PG2 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  753 00002000         ;//       <o2.3>     PG3 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  754 00002000         ;//       <o2.4>     PG4 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  755 00002000         ;//       <o2.5>     PG5 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  756 00002000         ;//       <o2.6>     PG6 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  757 00002000         ;//       <o2.7>     PG7 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  758 00002000         ;//       <o2.8>     PG8 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  759 00002000         ;//       <o2.9>     PG9 Pull-up         <0=> Enabled  <
                       1=> Disabled   
  760 00002000         ;//       <o2.10>    PG10 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  761 00002000         ;//       <o2.11>    PG11 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  762 00002000         ;//       <o2.12>    PG12 Pull-up        <0=> Enabled  <



ARM Macro Assembler    Page 23 


                       1=> Disabled   
  763 00002000         ;//       <o2.13>    PG13 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  764 00002000         ;//       <o2.14>    PG14 Pull-up        <0=> Enabled  <
                       1=> Disabled   
  765 00002000         ;//       <o2.15>    PG15 Pull-up        <0=> Enabled  <
                       1=> Disabled  
  766 00002000         ;//     </h>                                            
                               
  767 00002000         ;//   </e>
  768 00002000 00000001 
                       PIOG_SETUP
                               EQU              1
  769 00002000 FF4AFFB9 
                       PCONG_Val
                               EQU              0xff4affb9
  770 00002000 0000FFFF 
                       PUPG_Val
                               EQU              0xffff
  771 00002000         
  772 00002000         
  773 00002000         ;//   <e> Port H
  774 00002000         ;//     <o1.0..1>        PH0  <0=> Input   <1=> Output  
                       <2=> nCTS0    <3=> Reserved 
  775 00002000         ;//     <o1.2..3>        PH1  <0=> Input   <1=> Output  
                       <2=> nRTS0    <3=> Reserved 
  776 00002000         ;//     <o1.4..5>        PH2  <0=> Input   <1=> Output  
                       <2=> TXD[0]    <3=> Reserved 
  777 00002000         ;//     <o1.6..7>        PH3  <0=> Input   <1=> Output  
                       <2=> RXD[0]    <3=> Reserved 
  778 00002000         ;//     <o1.8..9>        PH4  <0=> Input   <1=> Output  
                       <2=> TXD[1]  <3=> Reserved 
  779 00002000         ;//     <o1.10..11>      PH5  <0=> Input   <1=> Output  
                       <2=> RXD[1]   <3=> Reserved 
  780 00002000         ;//     <o1.12..13>      PH6  <0=> Input   <1=> Output  
                       <2=> TXD[2]   <3=> nRTS1
  781 00002000         ;//     <o1.14..15>      PH7  <0=> Input   <1=> Output  
                       <2=> RXD[2]  <3=> nCTS1 
  782 00002000         ;//     <o1.16..17>      PH8  <0=> Input   <1=> Output  
                       <2=> UCLK    <3=> Reserved 
  783 00002000         ;//     <o1.18..19>      PH9  <0=> Input   <1=> Output  
                       <2=> CLKOUT0  <3=> Reserved 
  784 00002000         ;//     <o1.20..21>      PH10 <0=> Input   <1=> Output  
                       <2=> CLKOUT1  <3=> Reserved 
  785 00002000         ;//     <h> Pull-up Resistors                           
                                    
  786 00002000         ;//       <o2.0>    PH0 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  787 00002000         ;//       <o2.1>    PH1 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  788 00002000         ;//       <o2.2>    PH2 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  789 00002000         ;//       <o2.3>    PH3 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  790 00002000         ;//       <o2.4>    PH4 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  791 00002000         ;//       <o2.5>    PH5 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  792 00002000         ;//       <o2.6>    PH6 Pull-up        <0=> Enabled  <1=



ARM Macro Assembler    Page 24 


                       > Disabled   
  793 00002000         ;//       <o2.7>    PH7 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  794 00002000         ;//       <o2.8>    PH8 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  795 00002000         ;//       <o2.9>    PH9 Pull-up        <0=> Enabled  <1=
                       > Disabled   
  796 00002000         ;//       <o2.10>   PH10 Pull-up       <0=> Enabled  <1=
                       > Disabled   
  797 00002000         ;//     </h>                                            
                                    
  798 00002000         ;//   </e>
  799 00002000 00000001 
                       PIOH_SETUP
                               EQU              1
  800 00002000 002AFAAA 
                       PCONH_Val
                               EQU              0x2afaaa
  801 00002000 000007FF 
                       PUPH_Val
                               EQU              0x7ff
  802 00002000         
  803 00002000         ;// </e>
  804 00002000         
  805 00002000         
  806 00002000         
  807 00002000         
  808 00002000                 PRESERVE8
  809 00002000         
  810 00002000         
  811 00002000         ; Area Definition and Entry Point
  812 00002000         ;  Startup Code must be linked first at Address at which
                        it expects to run.
  813 00002000         
  814 00002000                 AREA             RESET, CODE, READONLY
  815 00000000                 ARM
  816 00000000         
  817 00000000         
  818 00000000         ; Exception Vectors
  819 00000000         ;  Mapped to Address 0.
  820 00000000         ;  Absolute addressing mode must be used.
  821 00000000         ;  Dummy Handlers are implemented as infinite loops whic
                       h can be modified.
  822 00000000         
  823 00000000 E59FF03C 
                       Vectors LDR              PC, Reset_Addr
  824 00000004 E59FF03C        LDR              PC, Undef_Addr
  825 00000008 E59FF03C        LDR              PC, SWI_Addr
  826 0000000C E59FF03C        LDR              PC, PAbt_Addr
  827 00000010 E59FF03C        LDR              PC, DAbt_Addr
  828 00000014 E1A00000        NOP                          ; Reserved Vector 
  829 00000018 E59FF03C        LDR              PC, IRQ_Addr
  830 0000001C E59FF03C        LDR              PC, FIQ_Addr
  831 00000020         
  832 00000020         
  833 00000020                 IF               IntVT_SETUP <> 0
  834 00000020         
  835 00000020         ;Interrupt Vector Table Address                
  836 00000020 33FFFF20 



ARM Macro Assembler    Page 25 


                       HandleEINT0
                               EQU              IntVTAddress
  837 00000020 33FFFF24 
                       HandleEINT1
                               EQU              IntVTAddress +4
  838 00000020 33FFFF28 
                       HandleEINT2
                               EQU              IntVTAddress +4*2
  839 00000020 33FFFF2C 
                       HandleEINT3
                               EQU              IntVTAddress +4*3
  840 00000020 33FFFF30 
                       HandleEINT4_7
                               EQU              IntVTAddress +4*4
  841 00000020 33FFFF34 
                       HandleEINT8_23
                               EQU              IntVTAddress +4*5
  842 00000020 33FFFF38 
                       HandleReserved
                               EQU              IntVTAddress +4*6
  843 00000020 33FFFF3C 
                       HandleBATFLT
                               EQU              IntVTAddress +4*7
  844 00000020 33FFFF40 
                       HandleTICK
                               EQU              IntVTAddress +4*8
  845 00000020 33FFFF44 
                       HandleWDT
                               EQU              IntVTAddress +4*9
  846 00000020 33FFFF48 
                       HandleTIMER0
                               EQU              IntVTAddress +4*10
  847 00000020 33FFFF4C 
                       HandleTIMER1
                               EQU              IntVTAddress +4*11
  848 00000020 33FFFF50 
                       HandleTIMER2
                               EQU              IntVTAddress +4*12
  849 00000020 33FFFF54 
                       HandleTIMER3
                               EQU              IntVTAddress +4*13
  850 00000020 33FFFF58 
                       HandleTIMER4
                               EQU              IntVTAddress +4*14
  851 00000020 33FFFF5C 
                       HandleUART2
                               EQU              IntVTAddress +4*15
  852 00000020 33FFFF60 
                       HandleLCD
                               EQU              IntVTAddress +4*16
  853 00000020 33FFFF64 
                       HandleDMA0
                               EQU              IntVTAddress +4*17
  854 00000020 33FFFF68 
                       HandleDMA1
                               EQU              IntVTAddress +4*18
  855 00000020 33FFFF6C 
                       HandleDMA2
                               EQU              IntVTAddress +4*19



ARM Macro Assembler    Page 26 


  856 00000020 33FFFF70 
                       HandleDMA3
                               EQU              IntVTAddress +4*20
  857 00000020 33FFFF74 
                       HandleMMC
                               EQU              IntVTAddress +4*21
  858 00000020 33FFFF78 
                       HandleSPI0
                               EQU              IntVTAddress +4*22
  859 00000020 33FFFF7C 
                       HandleUART1
                               EQU              IntVTAddress +4*23
  860 00000020         ;HandleReserved    EQU    IntVTAddress +4*24
  861 00000020 33FFFF84 
                       HandleUSBD
                               EQU              IntVTAddress +4*25
  862 00000020 33FFFF88 
                       HandleUSBH
                               EQU              IntVTAddress +4*26
  863 00000020 33FFFF8C 
                       HandleIIC
                               EQU              IntVTAddress +4*27
  864 00000020 33FFFF90 
                       HandleUART0
                               EQU              IntVTAddress +4*28
  865 00000020 33FFFFBC 
                       HandleSPI1
                               EQU              IntVTAddress +4*39
  866 00000020 33FFFF98 
                       HandleRTC
                               EQU              IntVTAddress +4*30
  867 00000020 33FFFF9C 
                       HandleADC
                               EQU              IntVTAddress +4*31
  868 00000020         
  869 00000020         IRQ_Entry
  870 00000020 E24DD004        sub              sp,sp,#4    ;reserved for PC
  871 00000024 E92D0300        stmfd            sp!,{r8-r9}
  872 00000028         
  873 00000028 E59F913C        ldr              r9,=INTOFFSET
  874 0000002C E5999000        ldr              r9,[r9]
  875 00000030 E59F8138        ldr              r8,=HandleEINT0
  876 00000034 E0888109        add              r8,r8,r9,lsl #2
  877 00000038 E5988000        ldr              r8,[r8]
  878 0000003C E58D8008        str              r8,[sp,#8]
  879 00000040 E8BD8300        ldmfd            sp!,{r8-r9,pc}
  880 00000044         
  881 00000044                 ENDIF
  882 00000044         
  883 00000044 00000000 
                       Reset_Addr
                               DCD              Reset_Handler
  884 00000048 00000000 
                       Undef_Addr
                               DCD              Undef_Handler
  885 0000004C 00000000 
                       SWI_Addr
                               DCD              SWI_Handler
  886 00000050 00000000 



ARM Macro Assembler    Page 27 


                       PAbt_Addr
                               DCD              PAbt_Handler
  887 00000054 00000000 
                       DAbt_Addr
                               DCD              DAbt_Handler
  888 00000058 00000000        DCD              0           ; Reserved Address 
                                                            
  889 0000005C 00000000 
                       IRQ_Addr
                               DCD              IRQ_Handler
  890 00000060 00000000 
                       FIQ_Addr
                               DCD              FIQ_Handler
  891 00000064         
  892 00000064 EAFFFFFE 
                       Undef_Handler
                               B                Undef_Handler
  893 00000068 EAFFFFFE 
                       SWI_Handler
                               B                SWI_Handler
  894 0000006C EAFFFFFE 
                       PAbt_Handler
                               B                PAbt_Handler
  895 00000070 EAFFFFFE 
                       DAbt_Handler
                               B                DAbt_Handler
  896 00000074         
  897 00000074                 IF               IntVT_SETUP <> 1
  899                          ENDIF
  900 00000074         
  901 00000074                 IF               IntVT_SETUP <> 0
  902 00000074 EAFFFFE9 
                       IRQ_Handler
                               B                IRQ_Entry
  903 00000078                 ENDIF
  904 00000078         
  905 00000078 EAFFFFFE 
                       FIQ_Handler
                               B                FIQ_Handler
  906 0000007C         
  907 0000007C         
  908 0000007C         
  909 0000007C         ; Memory Controller Configuration
  910 0000007C                 IF               MC_SETUP <> 0
  911 0000007C         MC_CFG
  912 0000007C 22111120        DCD              BWSCON_Val
  913 00000080 00000700        DCD              BANKCON0_Val
  914 00000084 00000700        DCD              BANKCON1_Val
  915 00000088 00000700        DCD              BANKCON2_Val
  916 0000008C 00000700        DCD              BANKCON3_Val
  917 00000090 00000700        DCD              BANKCON4_Val
  918 00000094 00000700        DCD              BANKCON5_Val
  919 00000098 00018005        DCD              BANKCON6_Val
  920 0000009C 00018005        DCD              BANKCON7_Val
  921 000000A0 008E0459        DCD              REFRESH_Val
  922 000000A4 000000B2        DCD              BANKSIZE_Val
  923 000000A8 00000030        DCD              MRSRB6_Val
  924 000000AC 00000030        DCD              MRSRB7_Val
  925 000000B0                 ENDIF



ARM Macro Assembler    Page 28 


  926 000000B0         
  927 000000B0         
  928 000000B0         ; Clock Management Configuration
  929 000000B0                 IF               CLK_SETUP <> 0
  930 000000B0         CLK_CFG
  931 000000B0 00FFFFFF        DCD              LOCKTIME_Val
  932 000000B4 00000003        DCD              CLKDIVN_Val
  933 000000B8 0005C042        DCD              MPLLCON_Val
  934 000000BC 00028080        DCD              UPLLCON_Val
  935 000000C0 00000004        DCD              CLKSLOW_Val
  936 000000C4 FFFFFFF0        DCD              CLKCON_Val
  937 000000C8                 ENDIF
  938 000000C8         
  939 000000C8         
  940 000000C8         
  941 000000C8         ; I/O Configuration
  942 000000C8                 IF               PIO_SETUP <> 0
  961                          ENDIF
  962 000000C8         
  963 000000C8         ; Reset Handler
  964 000000C8         
  965 000000C8                 EXPORT           Reset_Handler
  966 000000C8         Reset_Handler
  967 000000C8         
  968 000000C8                 IF               WT_SETUP <> 0
  969 000000C8 E3A00453        LDR              R0, =WT_BASE
  970 000000CC E3A01000        LDR              R1, =WTCON_Val
  971 000000D0 E59F209C        LDR              R2, =WTDAT_Val
  972 000000D4 E5802008        STR              R2, [R0, #WTCNT_OFS] ;Becuase W
                                                            TCNT and WTDAT have
                                                             the same defualt v
                                                            alue 
  973 000000D8 E5802004        STR              R2, [R0, #WTDAT_OFS]
  974 000000DC E5801000        STR              R1, [R0, #WTCON_OFS]
  975 000000E0                 ENDIF
  976 000000E0         
  977 000000E0                 IF               INT_SETUP <> 0
  978 000000E0 E3A0044A        LDR              R0, =INT_BASE
  979 000000E4 E3E01000        LDR              R1, =INTMASK_VAL
  980 000000E8 E59F2088        LDR              R2, =INTSUBMASK_VAL
  981 000000EC E5801008        STR              R1, [R0,#INTMASK_OFS]
  982 000000F0 E580201C        STR              R2, [R0,#INTSUBMASK_OFS]
  983 000000F4                 ENDIF
  984 000000F4         
  985 000000F4                 IF               CLK_SETUP <> 0
  986 000000F4 E3A00313        LDR              R0, =CLK_BASE
  987 000000F8 E24F8050        ADR              R8, CLK_CFG
  988 000000FC E898007E        LDMIA            R8, {R1-R6}
  989 00000100 E5801000        STR              R1, [R0, #LOCKTIME_OFS]
  990 00000104 E5802014        STR              R2, [R0, #CLKDIVN_OFS]
  991 00000108 E5803004        STR              R3, [R0, #MPLLCON_OFS]
  992 0000010C E5804008        STR              R4, [R0, #UPLLCON_OFS]
  993 00000110 E5805010        STR              R5, [R0, #CLKSLOW_OFS]
  994 00000114 E580600C        STR              R6, [R0, #CLKCON_OFS]
  995 00000118                 ENDIF
  996 00000118         
  997 00000118         
  998 00000118                 IF               MC_SETUP <> 0
  999 00000118 E24FD0A4        ADR              R13, MC_CFG



ARM Macro Assembler    Page 29 


 1000 0000011C E89D1FFF        LDMIA            R13, {R0-R12}
 1001 00000120 E3A0D312        LDR              R13, =MC_BASE
 1002 00000124 E88D1FFF        STMIA            R13, {R0-R12}
 1003 00000128                 ENDIF
 1004 00000128         
 1005 00000128         
 1006 00000128                 IF               PIO_SETUP <> 0
 1067                          ENDIF
 1068 00000128         
 1069 00000128         
 1070 00000128         ; Setup Stack for each mode
 1071 00000128         
 1072 00000128 E59F004C        LDR              R0, =Stack_Top
 1073 0000012C         
 1074 0000012C         ;  Enter Undefined Instruction Mode and set its Stack Po
                       inter
 1075 0000012C E321F0DB        MSR              CPSR_c, #Mode_UND:OR:I_Bit:OR:F
_Bit
 1076 00000130 E1A0D000        MOV              SP, R0
 1077 00000134 E2400B01        SUB              R0, R0, #UND_Stack_Size
 1078 00000138         
 1079 00000138         ;  Enter Abort Mode and set its Stack Pointer
 1080 00000138 E321F0D7        MSR              CPSR_c, #Mode_ABT:OR:I_Bit:OR:F
_Bit
 1081 0000013C E1A0D000        MOV              SP, R0
 1082 00000140 E2400B01        SUB              R0, R0, #ABT_Stack_Size
 1083 00000144         
 1084 00000144         ;  Enter FIQ Mode and set its Stack Pointer
 1085 00000144 E321F0D1        MSR              CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F
_Bit
 1086 00000148 E1A0D000        MOV              SP, R0
 1087 0000014C E2400A01        SUB              R0, R0, #FIQ_Stack_Size
 1088 00000150         
 1089 00000150         ;  Enter IRQ Mode and set its Stack Pointer
 1090 00000150 E321F0D2        MSR              CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F
_Bit
 1091 00000154 E1A0D000        MOV              SP, R0
 1092 00000158 E2400A01        SUB              R0, R0, #IRQ_Stack_Size
 1093 0000015C         
 1094 0000015C         ;  Enter Supervisor Mode and set its Stack Pointer
 1095 0000015C E321F0D3        MSR              CPSR_c, #Mode_SVC:OR:I_Bit:OR:F
_Bit
 1096 00000160 E1A0D000        MOV              SP, R0
 1097 00000164 E2400A01        SUB              R0, R0, #SVC_Stack_Size
 1098 00000168         
 1099 00000168         ;  Enter User Mode and set its Stack Pointer
 1100 00000168         ;                MSR     CPSR_c, #Mode_USR
 1101 00000168         ;                MOV     SP, R0
 1102 00000168         ;                SUB     SL, SP, #USR_Stack_Size
 1103 00000168         
 1104 00000168         
 1105 00000168         ; Enter the C code
 1106 00000168         
 1107 00000168                 IMPORT           __main
 1108 00000168         ; LDR     R0, =__main
 1109 00000168         ;  BX      R0
 1110 00000168 EBFFFFFE        BL               __main
 1111 0000016C         
 1112 0000016C         



ARM Macro Assembler    Page 30 


 1113 0000016C         ; User Initial Stack & Heap
 1114 0000016C 4A000014 
              33FFFF20 
              FFFF8000 
              000007FF 
              00000000         AREA             |.text|, CODE, READONLY
 1115 00000000         
 1116 00000000                 IMPORT           __use_two_region_memory
 1117 00000000                 EXPORT           __user_initial_stackheap
 1118 00000000         __user_initial_stackheap
 1119 00000000         
 1120 00000000 E59F000C        LDR              R0, =  Heap_Mem
 1121 00000004 E59F100C        LDR              R1, =(Stack_Mem + USR_Stack_Siz
e)
 1122 00000008 E59F200C        LDR              R2, = (Heap_Mem +      Heap_Siz
e)
 1123 0000000C E59F300C        LDR              R3, = Stack_Mem
 1124 00000010 E12FFF1E        BX               LR
 1125 00000014         
 1126 00000014         
 1127 00000014                 END
              00000000 
              00001000 
              00002000 
              00000000 
Command Line: --debug --xref --device=DARMSS9 --apcs=interwork -o.\obj\S3C2410A
.o -I..\common\inc -IC:\Keil\ARM\INC\Samsung --list=.\lst\S3C2410A.lst S3C2410A
.s



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

STACK 00000000

Symbol: STACK
   Definitions
      At line 50 in file S3C2410A.s
   Uses
      None
Comment: STACK unused
Stack_Mem 00000000

Symbol: Stack_Mem
   Definitions
      At line 51 in file S3C2410A.s
   Uses
      At line 53 in file S3C2410A.s
      At line 1121 in file S3C2410A.s
      At line 1123 in file S3C2410A.s

Stack_Top 00004800

Symbol: Stack_Top
   Definitions
      At line 53 in file S3C2410A.s
   Uses
      At line 1072 in file S3C2410A.s
Comment: Stack_Top used once
3 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

HEAP 00000000

Symbol: HEAP
   Definitions
      At line 62 in file S3C2410A.s
   Uses
      None
Comment: HEAP unused
Heap_Mem 00000000

Symbol: Heap_Mem
   Definitions
      At line 63 in file S3C2410A.s
   Uses
      At line 1120 in file S3C2410A.s
      At line 1122 in file S3C2410A.s

2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

CLK_CFG 000000B0

Symbol: CLK_CFG
   Definitions
      At line 930 in file S3C2410A.s
   Uses
      At line 987 in file S3C2410A.s
Comment: CLK_CFG used once
DAbt_Addr 00000054

Symbol: DAbt_Addr
   Definitions
      At line 887 in file S3C2410A.s
   Uses
      At line 827 in file S3C2410A.s
Comment: DAbt_Addr used once
DAbt_Handler 00000070

Symbol: DAbt_Handler
   Definitions
      At line 895 in file S3C2410A.s
   Uses
      At line 887 in file S3C2410A.s
      At line 895 in file S3C2410A.s

FIQ_Addr 00000060

Symbol: FIQ_Addr
   Definitions
      At line 890 in file S3C2410A.s
   Uses
      At line 830 in file S3C2410A.s
Comment: FIQ_Addr used once
FIQ_Handler 00000078

Symbol: FIQ_Handler
   Definitions
      At line 905 in file S3C2410A.s
   Uses
      At line 890 in file S3C2410A.s
      At line 905 in file S3C2410A.s

IRQ_Addr 0000005C

Symbol: IRQ_Addr
   Definitions
      At line 889 in file S3C2410A.s
   Uses
      At line 829 in file S3C2410A.s
Comment: IRQ_Addr used once
IRQ_Entry 00000020

Symbol: IRQ_Entry
   Definitions
      At line 869 in file S3C2410A.s
   Uses
      At line 902 in file S3C2410A.s
Comment: IRQ_Entry used once
IRQ_Handler 00000074



ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Relocatable symbols


Symbol: IRQ_Handler
   Definitions
      At line 902 in file S3C2410A.s
   Uses
      At line 889 in file S3C2410A.s
Comment: IRQ_Handler used once
MC_CFG 0000007C

Symbol: MC_CFG
   Definitions
      At line 911 in file S3C2410A.s
   Uses
      At line 999 in file S3C2410A.s
Comment: MC_CFG used once
PAbt_Addr 00000050

Symbol: PAbt_Addr
   Definitions
      At line 886 in file S3C2410A.s
   Uses
      At line 826 in file S3C2410A.s
Comment: PAbt_Addr used once
PAbt_Handler 0000006C

Symbol: PAbt_Handler
   Definitions
      At line 894 in file S3C2410A.s
   Uses
      At line 886 in file S3C2410A.s
      At line 894 in file S3C2410A.s

RESET 00000000

Symbol: RESET
   Definitions
      At line 814 in file S3C2410A.s
   Uses
      None
Comment: RESET unused
Reset_Addr 00000044

Symbol: Reset_Addr
   Definitions
      At line 883 in file S3C2410A.s
   Uses
      At line 823 in file S3C2410A.s
Comment: Reset_Addr used once
Reset_Handler 000000C8

Symbol: Reset_Handler
   Definitions
      At line 966 in file S3C2410A.s
   Uses
      At line 883 in file S3C2410A.s
      At line 965 in file S3C2410A.s

SWI_Addr 0000004C




ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Relocatable symbols

Symbol: SWI_Addr
   Definitions
      At line 885 in file S3C2410A.s
   Uses
      At line 825 in file S3C2410A.s
Comment: SWI_Addr used once
SWI_Handler 00000068

Symbol: SWI_Handler
   Definitions
      At line 893 in file S3C2410A.s
   Uses
      At line 885 in file S3C2410A.s
      At line 893 in file S3C2410A.s

Undef_Addr 00000048

Symbol: Undef_Addr
   Definitions
      At line 884 in file S3C2410A.s
   Uses
      At line 824 in file S3C2410A.s
Comment: Undef_Addr used once
Undef_Handler 00000064

Symbol: Undef_Handler
   Definitions
      At line 892 in file S3C2410A.s
   Uses
      At line 884 in file S3C2410A.s
      At line 892 in file S3C2410A.s

Vectors 00000000

Symbol: Vectors
   Definitions
      At line 823 in file S3C2410A.s
   Uses
      None
Comment: Vectors unused
19 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.text 00000000

Symbol: .text
   Definitions
      At line 1114 in file S3C2410A.s
   Uses
      None
Comment: .text unused
__user_initial_stackheap 00000000

Symbol: __user_initial_stackheap
   Definitions
      At line 1118 in file S3C2410A.s
   Uses
      At line 1117 in file S3C2410A.s
Comment: __user_initial_stackheap used once
2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_info$$$RESET 00000000

Symbol: .debug_info$$$RESET
   Definitions
      None
   Uses
      None
Warning: .debug_info$$$RESET undefinedComment: .debug_info$$$RESET unused
1 symbol



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_line$$$RESET 00000000

Symbol: .debug_line$$$RESET
   Definitions
      None
   Uses
      None
Warning: .debug_line$$$RESET undefinedComment: .debug_line$$$RESET unused
1 symbol



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_info$$$.text 00000000

Symbol: .debug_info$$$.text
   Definitions
      None
   Uses
      None
Warning: .debug_info$$$.text undefinedComment: .debug_info$$$.text unused
1 symbol



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_line$$$.text 00000000

Symbol: .debug_line$$$.text
   Definitions
      None
   Uses
      None
Warning: .debug_line$$$.text undefinedComment: .debug_line$$$.text unused
1 symbol



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

.debug_abbrev 00000000

Symbol: .debug_abbrev
   Definitions
      None
   Uses
      None
Warning: .debug_abbrev undefinedComment: .debug_abbrev unused
__ARM_asm.debug_abbrev 00000000

Symbol: __ARM_asm.debug_abbrev
   Definitions
      None
   Uses
      None
Warning: __ARM_asm.debug_abbrev undefinedComment: __ARM_asm.debug_abbrev unused
2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Absolute symbols

ABT_Stack_Size 00000400

Symbol: ABT_Stack_Size
   Definitions
      At line 42 in file S3C2410A.s
   Uses
      At line 48 in file S3C2410A.s
      At line 1082 in file S3C2410A.s

BANKCON0_Val 00000700

Symbol: BANKCON0_Val
   Definitions
      At line 476 in file S3C2410A.s
   Uses
      At line 913 in file S3C2410A.s
Comment: BANKCON0_Val used once
BANKCON1_Val 00000700

Symbol: BANKCON1_Val
   Definitions
      At line 477 in file S3C2410A.s
   Uses
      At line 914 in file S3C2410A.s
Comment: BANKCON1_Val used once
BANKCON2_Val 00000700

Symbol: BANKCON2_Val
   Definitions
      At line 478 in file S3C2410A.s
   Uses
      At line 915 in file S3C2410A.s
Comment: BANKCON2_Val used once
BANKCON3_Val 00000700

Symbol: BANKCON3_Val
   Definitions
      At line 479 in file S3C2410A.s
   Uses
      At line 916 in file S3C2410A.s
Comment: BANKCON3_Val used once
BANKCON4_Val 00000700

Symbol: BANKCON4_Val
   Definitions
      At line 480 in file S3C2410A.s
   Uses
      At line 917 in file S3C2410A.s
Comment: BANKCON4_Val used once
BANKCON5_Val 00000700

Symbol: BANKCON5_Val
   Definitions
      At line 481 in file S3C2410A.s
   Uses
      At line 918 in file S3C2410A.s
Comment: BANKCON5_Val used once
BANKCON6_Val 00018005




ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Absolute symbols

Symbol: BANKCON6_Val
   Definitions
      At line 482 in file S3C2410A.s
   Uses
      At line 919 in file S3C2410A.s
Comment: BANKCON6_Val used once
BANKCON7_Val 00018005

Symbol: BANKCON7_Val
   Definitions
      At line 483 in file S3C2410A.s
   Uses
      At line 920 in file S3C2410A.s
Comment: BANKCON7_Val used once
BANKSIZE_Val 000000B2

Symbol: BANKSIZE_Val
   Definitions
      At line 486 in file S3C2410A.s
   Uses
      At line 922 in file S3C2410A.s
Comment: BANKSIZE_Val used once
BWSCON_Val 22111120

Symbol: BWSCON_Val
   Definitions
      At line 484 in file S3C2410A.s
   Uses
      At line 912 in file S3C2410A.s
Comment: BWSCON_Val used once
CAMDIVN_OFS 00000018

Symbol: CAMDIVN_OFS
   Definitions
      At line 82 in file S3C2410A.s
   Uses
      None
Comment: CAMDIVN_OFS unused
CLKCON_OFS 0000000C

Symbol: CLKCON_OFS
   Definitions
      At line 79 in file S3C2410A.s
   Uses
      At line 994 in file S3C2410A.s
Comment: CLKCON_OFS used once
CLKCON_Val FFFFFFF0

Symbol: CLKCON_Val
   Definitions
      At line 150 in file S3C2410A.s
   Uses
      At line 936 in file S3C2410A.s
Comment: CLKCON_Val used once
CLKDIVN_OFS 00000014

Symbol: CLKDIVN_OFS
   Definitions
      At line 81 in file S3C2410A.s



ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 990 in file S3C2410A.s
Comment: CLKDIVN_OFS used once
CLKDIVN_Val 00000003

Symbol: CLKDIVN_Val
   Definitions
      At line 153 in file S3C2410A.s
   Uses
      At line 932 in file S3C2410A.s
Comment: CLKDIVN_Val used once
CLKSLOW_OFS 00000010

Symbol: CLKSLOW_OFS
   Definitions
      At line 80 in file S3C2410A.s
   Uses
      At line 993 in file S3C2410A.s
Comment: CLKSLOW_OFS used once
CLKSLOW_Val 00000004

Symbol: CLKSLOW_Val
   Definitions
      At line 151 in file S3C2410A.s
   Uses
      At line 935 in file S3C2410A.s
Comment: CLKSLOW_Val used once
CLK_BASE 4C000000

Symbol: CLK_BASE
   Definitions
      At line 75 in file S3C2410A.s
   Uses
      At line 986 in file S3C2410A.s
Comment: CLK_BASE used once
CLK_SETUP 00000001

Symbol: CLK_SETUP
   Definitions
      At line 147 in file S3C2410A.s
   Uses
      At line 929 in file S3C2410A.s
      At line 985 in file S3C2410A.s

FIQ_Stack_Size 00001000

Symbol: FIQ_Stack_Size
   Definitions
      At line 43 in file S3C2410A.s
   Uses
      At line 48 in file S3C2410A.s
      At line 1087 in file S3C2410A.s

F_Bit 00000040

Symbol: F_Bit
   Definitions
      At line 28 in file S3C2410A.s
   Uses



ARM Macro Assembler    Page 4 Alphabetic symbol ordering
Absolute symbols

      At line 1075 in file S3C2410A.s
      At line 1080 in file S3C2410A.s
      At line 1085 in file S3C2410A.s
      At line 1090 in file S3C2410A.s
      At line 1095 in file S3C2410A.s

HandleADC 33FFFF9C

Symbol: HandleADC
   Definitions
      At line 867 in file S3C2410A.s
   Uses
      None
Comment: HandleADC unused
HandleBATFLT 33FFFF3C

Symbol: HandleBATFLT
   Definitions
      At line 843 in file S3C2410A.s
   Uses
      None
Comment: HandleBATFLT unused
HandleDMA0 33FFFF64

Symbol: HandleDMA0
   Definitions
      At line 853 in file S3C2410A.s
   Uses
      None
Comment: HandleDMA0 unused
HandleDMA1 33FFFF68

Symbol: HandleDMA1
   Definitions
      At line 854 in file S3C2410A.s
   Uses
      None
Comment: HandleDMA1 unused
HandleDMA2 33FFFF6C

Symbol: HandleDMA2
   Definitions
      At line 855 in file S3C2410A.s
   Uses
      None
Comment: HandleDMA2 unused
HandleDMA3 33FFFF70

Symbol: HandleDMA3
   Definitions
      At line 856 in file S3C2410A.s
   Uses
      None
Comment: HandleDMA3 unused
HandleEINT0 33FFFF20

Symbol: HandleEINT0
   Definitions
      At line 836 in file S3C2410A.s



ARM Macro Assembler    Page 5 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 875 in file S3C2410A.s
Comment: HandleEINT0 used once
HandleEINT1 33FFFF24

Symbol: HandleEINT1
   Definitions
      At line 837 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT1 unused
HandleEINT2 33FFFF28

Symbol: HandleEINT2
   Definitions
      At line 838 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT2 unused
HandleEINT3 33FFFF2C

Symbol: HandleEINT3
   Definitions
      At line 839 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT3 unused
HandleEINT4_7 33FFFF30

Symbol: HandleEINT4_7
   Definitions
      At line 840 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT4_7 unused
HandleEINT8_23 33FFFF34

Symbol: HandleEINT8_23
   Definitions
      At line 841 in file S3C2410A.s
   Uses
      None
Comment: HandleEINT8_23 unused
HandleIIC 33FFFF8C

Symbol: HandleIIC
   Definitions
      At line 863 in file S3C2410A.s
   Uses
      None
Comment: HandleIIC unused
HandleLCD 33FFFF60

Symbol: HandleLCD
   Definitions
      At line 852 in file S3C2410A.s
   Uses
      None
Comment: HandleLCD unused



ARM Macro Assembler    Page 6 Alphabetic symbol ordering
Absolute symbols

HandleMMC 33FFFF74

Symbol: HandleMMC
   Definitions
      At line 857 in file S3C2410A.s
   Uses
      None
Comment: HandleMMC unused
HandleRTC 33FFFF98

Symbol: HandleRTC
   Definitions
      At line 866 in file S3C2410A.s
   Uses
      None
Comment: HandleRTC unused
HandleReserved 33FFFF38

Symbol: HandleReserved
   Definitions
      At line 842 in file S3C2410A.s
   Uses
      None
Comment: HandleReserved unused
HandleSPI0 33FFFF78

Symbol: HandleSPI0
   Definitions
      At line 858 in file S3C2410A.s
   Uses
      None
Comment: HandleSPI0 unused
HandleSPI1 33FFFFBC

Symbol: HandleSPI1
   Definitions
      At line 865 in file S3C2410A.s
   Uses
      None
Comment: HandleSPI1 unused
HandleTICK 33FFFF40

Symbol: HandleTICK
   Definitions
      At line 844 in file S3C2410A.s
   Uses
      None
Comment: HandleTICK unused
HandleTIMER0 33FFFF48

Symbol: HandleTIMER0
   Definitions
      At line 846 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER0 unused
HandleTIMER1 33FFFF4C

Symbol: HandleTIMER1



ARM Macro Assembler    Page 7 Alphabetic symbol ordering
Absolute symbols

   Definitions
      At line 847 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER1 unused
HandleTIMER2 33FFFF50

Symbol: HandleTIMER2
   Definitions
      At line 848 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER2 unused
HandleTIMER3 33FFFF54

Symbol: HandleTIMER3
   Definitions
      At line 849 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER3 unused
HandleTIMER4 33FFFF58

Symbol: HandleTIMER4
   Definitions
      At line 850 in file S3C2410A.s
   Uses
      None
Comment: HandleTIMER4 unused
HandleUART0 33FFFF90

Symbol: HandleUART0
   Definitions
      At line 864 in file S3C2410A.s
   Uses
      None
Comment: HandleUART0 unused
HandleUART1 33FFFF7C

Symbol: HandleUART1
   Definitions
      At line 859 in file S3C2410A.s
   Uses
      None
Comment: HandleUART1 unused
HandleUART2 33FFFF5C

Symbol: HandleUART2
   Definitions
      At line 851 in file S3C2410A.s
   Uses
      None
Comment: HandleUART2 unused
HandleUSBD 33FFFF84

Symbol: HandleUSBD
   Definitions
      At line 861 in file S3C2410A.s
   Uses



ARM Macro Assembler    Page 8 Alphabetic symbol ordering
Absolute symbols

      None
Comment: HandleUSBD unused
HandleUSBH 33FFFF88

Symbol: HandleUSBH
   Definitions
      At line 862 in file S3C2410A.s
   Uses
      None
Comment: HandleUSBH unused
HandleWDT 33FFFF44

Symbol: HandleWDT
   Definitions
      At line 845 in file S3C2410A.s
   Uses
      None
Comment: HandleWDT unused
Heap_Size 00002000

Symbol: Heap_Size
   Definitions
      At line 60 in file S3C2410A.s
   Uses
      At line 63 in file S3C2410A.s
      At line 1122 in file S3C2410A.s

INTMASK_OFS 00000008

Symbol: INTMASK_OFS
   Definitions
      At line 67 in file S3C2410A.s
   Uses
      At line 981 in file S3C2410A.s
Comment: INTMASK_OFS used once
INTMASK_VAL FFFFFFFF

Symbol: INTMASK_VAL
   Definitions
      At line 71 in file S3C2410A.s
   Uses
      At line 979 in file S3C2410A.s
Comment: INTMASK_VAL used once
INTOFFSET 4A000014

Symbol: INTOFFSET
   Definitions
      At line 158 in file S3C2410A.s
   Uses
      At line 873 in file S3C2410A.s
Comment: INTOFFSET used once
INTSUBMASK_OFS 0000001C

Symbol: INTSUBMASK_OFS
   Definitions
      At line 68 in file S3C2410A.s
   Uses
      At line 982 in file S3C2410A.s
Comment: INTSUBMASK_OFS used once



ARM Macro Assembler    Page 9 Alphabetic symbol ordering
Absolute symbols

INTSUBMASK_VAL 000007FF

Symbol: INTSUBMASK_VAL
   Definitions
      At line 72 in file S3C2410A.s
   Uses
      At line 980 in file S3C2410A.s
Comment: INTSUBMASK_VAL used once
INT_BASE 4A000000

Symbol: INT_BASE
   Definitions
      At line 66 in file S3C2410A.s
   Uses
      At line 978 in file S3C2410A.s
Comment: INT_BASE used once
INT_SETUP 00000001

Symbol: INT_SETUP
   Definitions
      At line 70 in file S3C2410A.s
   Uses
      At line 977 in file S3C2410A.s
Comment: INT_SETUP used once
IRQ_Stack_Size 00001000

Symbol: IRQ_Stack_Size
   Definitions
      At line 44 in file S3C2410A.s
   Uses
      At line 48 in file S3C2410A.s
      At line 1092 in file S3C2410A.s

I_Bit 00000080

Symbol: I_Bit
   Definitions
      At line 27 in file S3C2410A.s
   Uses
      At line 1075 in file S3C2410A.s
      At line 1080 in file S3C2410A.s
      At line 1085 in file S3C2410A.s
      At line 1090 in file S3C2410A.s
      At line 1095 in file S3C2410A.s

IntVTAddress 33FFFF20

Symbol: IntVTAddress
   Definitions
      At line 166 in file S3C2410A.s
   Uses
      At line 836 in file S3C2410A.s
      At line 837 in file S3C2410A.s
      At line 838 in file S3C2410A.s
      At line 839 in file S3C2410A.s
      At line 840 in file S3C2410A.s
      At line 841 in file S3C2410A.s
      At line 842 in file S3C2410A.s
      At line 843 in file S3C2410A.s



ARM Macro Assembler    Page 10 Alphabetic symbol ordering
Absolute symbols

      At line 844 in file S3C2410A.s
      At line 845 in file S3C2410A.s
      At line 846 in file S3C2410A.s
      At line 847 in file S3C2410A.s
      At line 848 in file S3C2410A.s
      At line 849 in file S3C2410A.s
      At line 850 in file S3C2410A.s
      At line 851 in file S3C2410A.s
      At line 852 in file S3C2410A.s
      At line 853 in file S3C2410A.s
      At line 854 in file S3C2410A.s
      At line 855 in file S3C2410A.s
      At line 856 in file S3C2410A.s
      At line 857 in file S3C2410A.s
      At line 858 in file S3C2410A.s
      At line 859 in file S3C2410A.s
      At line 861 in file S3C2410A.s
      At line 862 in file S3C2410A.s
      At line 863 in file S3C2410A.s
      At line 864 in file S3C2410A.s
      At line 865 in file S3C2410A.s
      At line 866 in file S3C2410A.s
      At line 867 in file S3C2410A.s

IntVT_SETUP 00000001

Symbol: IntVT_SETUP
   Definitions
      At line 165 in file S3C2410A.s
   Uses
      At line 833 in file S3C2410A.s
      At line 897 in file S3C2410A.s
      At line 901 in file S3C2410A.s

LOCKTIME_OFS 00000000

Symbol: LOCKTIME_OFS
   Definitions
      At line 76 in file S3C2410A.s
   Uses
      At line 989 in file S3C2410A.s
Comment: LOCKTIME_OFS used once
LOCKTIME_Val 00FFFFFF

Symbol: LOCKTIME_Val
   Definitions
      At line 152 in file S3C2410A.s
   Uses
      At line 931 in file S3C2410A.s
Comment: LOCKTIME_Val used once
MC_BASE 48000000

Symbol: MC_BASE
   Definitions
      At line 190 in file S3C2410A.s
   Uses
      At line 1001 in file S3C2410A.s
Comment: MC_BASE used once
MC_SETUP 00000001



ARM Macro Assembler    Page 11 Alphabetic symbol ordering
Absolute symbols


Symbol: MC_SETUP
   Definitions
      At line 193 in file S3C2410A.s
   Uses
      At line 910 in file S3C2410A.s
      At line 998 in file S3C2410A.s

MPLLCON_OFS 00000004

Symbol: MPLLCON_OFS
   Definitions
      At line 77 in file S3C2410A.s
   Uses
      At line 991 in file S3C2410A.s
Comment: MPLLCON_OFS used once
MPLLCON_Val 0005C042

Symbol: MPLLCON_Val
   Definitions
      At line 148 in file S3C2410A.s
   Uses
      At line 933 in file S3C2410A.s
Comment: MPLLCON_Val used once
MRSRB6_Val 00000030

Symbol: MRSRB6_Val
   Definitions
      At line 487 in file S3C2410A.s
   Uses
      At line 923 in file S3C2410A.s
Comment: MRSRB6_Val used once
MRSRB7_Val 00000030

Symbol: MRSRB7_Val
   Definitions
      At line 488 in file S3C2410A.s
   Uses
      At line 924 in file S3C2410A.s
Comment: MRSRB7_Val used once
Mode_ABT 00000017

Symbol: Mode_ABT
   Definitions
      At line 23 in file S3C2410A.s
   Uses
      At line 1080 in file S3C2410A.s
Comment: Mode_ABT used once
Mode_FIQ 00000011

Symbol: Mode_FIQ
   Definitions
      At line 20 in file S3C2410A.s
   Uses
      At line 1085 in file S3C2410A.s
Comment: Mode_FIQ used once
Mode_IRQ 00000012

Symbol: Mode_IRQ



ARM Macro Assembler    Page 12 Alphabetic symbol ordering
Absolute symbols

   Definitions
      At line 21 in file S3C2410A.s
   Uses
      At line 1090 in file S3C2410A.s
Comment: Mode_IRQ used once
Mode_SVC 00000013

Symbol: Mode_SVC
   Definitions
      At line 22 in file S3C2410A.s
   Uses
      At line 1095 in file S3C2410A.s
Comment: Mode_SVC used once
Mode_SYS 0000001F

Symbol: Mode_SYS
   Definitions
      At line 25 in file S3C2410A.s
   Uses
      None
Comment: Mode_SYS unused
Mode_UND 0000001B

Symbol: Mode_UND
   Definitions
      At line 24 in file S3C2410A.s
   Uses
      At line 1075 in file S3C2410A.s
Comment: Mode_UND used once
Mode_USR 00000010

Symbol: Mode_USR
   Definitions
      At line 19 in file S3C2410A.s
   Uses
      None
Comment: Mode_USR unused
PCONA_OFS 00000000

Symbol: PCONA_OFS
   Definitions
      At line 496 in file S3C2410A.s
   Uses
      None
Comment: PCONA_OFS unused
PCONA_Val 005EF7FF

Symbol: PCONA_Val
   Definitions
      At line 554 in file S3C2410A.s
   Uses
      None
Comment: PCONA_Val unused
PCONB_OFS 00000010

Symbol: PCONB_OFS
   Definitions
      At line 497 in file S3C2410A.s
   Uses



ARM Macro Assembler    Page 13 Alphabetic symbol ordering
Absolute symbols

      None
Comment: PCONB_OFS unused
PCONB_Val 00155559

Symbol: PCONB_Val
   Definitions
      At line 583 in file S3C2410A.s
   Uses
      None
Comment: PCONB_Val unused
PCONC_OFS 00000020

Symbol: PCONC_OFS
   Definitions
      At line 498 in file S3C2410A.s
   Uses
      None
Comment: PCONC_OFS unused
PCONC_Val AAAA55AA

Symbol: PCONC_Val
   Definitions
      At line 623 in file S3C2410A.s
   Uses
      None
Comment: PCONC_Val unused
PCOND_OFS 00000030

Symbol: PCOND_OFS
   Definitions
      At line 499 in file S3C2410A.s
   Uses
      None
Comment: PCOND_OFS unused
PCOND_Val AAAAAAAA

Symbol: PCOND_Val
   Definitions
      At line 664 in file S3C2410A.s
   Uses
      None
Comment: PCOND_Val unused
PCONE_OFS 00000040

Symbol: PCONE_OFS
   Definitions
      At line 500 in file S3C2410A.s
   Uses
      None
Comment: PCONE_OFS unused
PCONE_Val AAAAAAAA

Symbol: PCONE_Val
   Definitions
      At line 704 in file S3C2410A.s
   Uses
      None
Comment: PCONE_Val unused
PCONF_OFS 00000050



ARM Macro Assembler    Page 14 Alphabetic symbol ordering
Absolute symbols


Symbol: PCONF_OFS
   Definitions
      At line 501 in file S3C2410A.s
   Uses
      None
Comment: PCONF_OFS unused
PCONF_Val 000055AA

Symbol: PCONF_Val
   Definitions
      At line 728 in file S3C2410A.s
   Uses
      None
Comment: PCONF_Val unused
PCONG_OFS 00000060

Symbol: PCONG_OFS
   Definitions
      At line 502 in file S3C2410A.s
   Uses
      None
Comment: PCONG_OFS unused
PCONG_Val FF4AFFB9

Symbol: PCONG_Val
   Definitions
      At line 769 in file S3C2410A.s
   Uses
      None
Comment: PCONG_Val unused
PCONH_OFS 00000070

Symbol: PCONH_OFS
   Definitions
      At line 503 in file S3C2410A.s
   Uses
      None
Comment: PCONH_OFS unused
PCONH_Val 002AFAAA

Symbol: PCONH_Val
   Definitions
      At line 800 in file S3C2410A.s
   Uses
      None
Comment: PCONH_Val unused
PDAA_OFS 00000004

Symbol: PDAA_OFS
   Definitions
      At line 513 in file S3C2410A.s
   Uses
      None
Comment: PDAA_OFS unused
PDAB_OFS 00000014

Symbol: PDAB_OFS
   Definitions



ARM Macro Assembler    Page 15 Alphabetic symbol ordering
Absolute symbols

      At line 514 in file S3C2410A.s
   Uses
      None
Comment: PDAB_OFS unused
PDAC_OFS 00000024

Symbol: PDAC_OFS
   Definitions
      At line 515 in file S3C2410A.s
   Uses
      None
Comment: PDAC_OFS unused
PDAC_Val 00000000

Symbol: PDAC_Val
   Definitions
      At line 625 in file S3C2410A.s
   Uses
      None
Comment: PDAC_Val unused
PDAD_OFS 00000034

Symbol: PDAD_OFS
   Definitions
      At line 516 in file S3C2410A.s
   Uses
      None
Comment: PDAD_OFS unused
PDAE_OFS 00000044

Symbol: PDAE_OFS
   Definitions
      At line 517 in file S3C2410A.s
   Uses
      None
Comment: PDAE_OFS unused
PDAF_OFS 00000054

Symbol: PDAF_OFS
   Definitions
      At line 518 in file S3C2410A.s
   Uses
      None
Comment: PDAF_OFS unused
PDAF_Val 0000000F

Symbol: PDAF_Val
   Definitions
      At line 730 in file S3C2410A.s
   Uses
      None
Comment: PDAF_Val unused
PDAG_OFS 00000064

Symbol: PDAG_OFS
   Definitions
      At line 519 in file S3C2410A.s
   Uses
      None



ARM Macro Assembler    Page 16 Alphabetic symbol ordering
Absolute symbols

Comment: PDAG_OFS unused
PDAH_OFS 00000074

Symbol: PDAH_OFS
   Definitions
      At line 520 in file S3C2410A.s
   Uses
      None
Comment: PDAH_OFS unused
PIOA_SETUP 00000001

Symbol: PIOA_SETUP
   Definitions
      At line 553 in file S3C2410A.s
   Uses
      None
Comment: PIOA_SETUP unused
PIOB_SETUP 00000001

Symbol: PIOB_SETUP
   Definitions
      At line 582 in file S3C2410A.s
   Uses
      None
Comment: PIOB_SETUP unused
PIOC_SETUP 00000001

Symbol: PIOC_SETUP
   Definitions
      At line 622 in file S3C2410A.s
   Uses
      None
Comment: PIOC_SETUP unused
PIOD_SETUP 00000001

Symbol: PIOD_SETUP
   Definitions
      At line 663 in file S3C2410A.s
   Uses
      None
Comment: PIOD_SETUP unused
PIOE_SETUP 00000001

Symbol: PIOE_SETUP
   Definitions
      At line 703 in file S3C2410A.s
   Uses
      None
Comment: PIOE_SETUP unused
PIOF_SETUP 00000001

Symbol: PIOF_SETUP
   Definitions
      At line 727 in file S3C2410A.s
   Uses
      None
Comment: PIOF_SETUP unused
PIOG_SETUP 00000001




ARM Macro Assembler    Page 17 Alphabetic symbol ordering
Absolute symbols

Symbol: PIOG_SETUP
   Definitions
      At line 768 in file S3C2410A.s
   Uses
      None
Comment: PIOG_SETUP unused
PIOH_SETUP 00000001

Symbol: PIOH_SETUP
   Definitions
      At line 799 in file S3C2410A.s
   Uses
      None
Comment: PIOH_SETUP unused
PIO_BASE 56000000

Symbol: PIO_BASE
   Definitions
      At line 495 in file S3C2410A.s
   Uses
      None
Comment: PIO_BASE unused
PIO_SETUP 00000000

Symbol: PIO_SETUP
   Definitions
      At line 526 in file S3C2410A.s
   Uses
      At line 942 in file S3C2410A.s
      At line 1006 in file S3C2410A.s

PUPB_OFS 00000018

Symbol: PUPB_OFS
   Definitions
      At line 505 in file S3C2410A.s
   Uses
      None
Comment: PUPB_OFS unused
PUPB_Val 000007FF

Symbol: PUPB_Val
   Definitions
      At line 584 in file S3C2410A.s
   Uses
      None
Comment: PUPB_Val unused
PUPC_OFS 00000028

Symbol: PUPC_OFS
   Definitions
      At line 506 in file S3C2410A.s
   Uses
      None
Comment: PUPC_OFS unused
PUPC_Val 0000FFFF

Symbol: PUPC_Val
   Definitions



ARM Macro Assembler    Page 18 Alphabetic symbol ordering
Absolute symbols

      At line 624 in file S3C2410A.s
   Uses
      None
Comment: PUPC_Val unused
PUPD_OFS 00000038

Symbol: PUPD_OFS
   Definitions
      At line 507 in file S3C2410A.s
   Uses
      None
Comment: PUPD_OFS unused
PUPD_Val 0000FFFF

Symbol: PUPD_Val
   Definitions
      At line 665 in file S3C2410A.s
   Uses
      None
Comment: PUPD_Val unused
PUPE_OFS 00000048

Symbol: PUPE_OFS
   Definitions
      At line 508 in file S3C2410A.s
   Uses
      None
Comment: PUPE_OFS unused
PUPE_Val 0000FFFF

Symbol: PUPE_Val
   Definitions
      At line 705 in file S3C2410A.s
   Uses
      None
Comment: PUPE_Val unused
PUPF_OFS 00000058

Symbol: PUPF_OFS
   Definitions
      At line 509 in file S3C2410A.s
   Uses
      None
Comment: PUPF_OFS unused
PUPF_Val 000000FF

Symbol: PUPF_Val
   Definitions
      At line 729 in file S3C2410A.s
   Uses
      None
Comment: PUPF_Val unused
PUPG_OFS 00000068

Symbol: PUPG_OFS
   Definitions
      At line 510 in file S3C2410A.s
   Uses
      None



ARM Macro Assembler    Page 19 Alphabetic symbol ordering
Absolute symbols

Comment: PUPG_OFS unused
PUPG_Val 0000FFFF

Symbol: PUPG_Val
   Definitions
      At line 770 in file S3C2410A.s
   Uses
      None
Comment: PUPG_Val unused
PUPH_OFS 00000078

Symbol: PUPH_OFS
   Definitions
      At line 511 in file S3C2410A.s
   Uses
      None
Comment: PUPH_OFS unused
PUPH_Val 000007FF

Symbol: PUPH_Val
   Definitions
      At line 801 in file S3C2410A.s
   Uses
      None
Comment: PUPH_Val unused
PUPJ_OFS 000000D8

Symbol: PUPJ_OFS
   Definitions
      At line 512 in file S3C2410A.s
   Uses
      None
Comment: PUPJ_OFS unused
REFRESH_Val 008E0459

Symbol: REFRESH_Val
   Definitions
      At line 485 in file S3C2410A.s
   Uses
      At line 921 in file S3C2410A.s
Comment: REFRESH_Val used once
SVC_Stack_Size 00001000

Symbol: SVC_Stack_Size
   Definitions
      At line 41 in file S3C2410A.s
   Uses
      At line 48 in file S3C2410A.s
      At line 1097 in file S3C2410A.s

Stack_Size 00004800

Symbol: Stack_Size
   Definitions
      At line 48 in file S3C2410A.s
   Uses
      At line 51 in file S3C2410A.s
      At line 53 in file S3C2410A.s




ARM Macro Assembler    Page 20 Alphabetic symbol ordering
Absolute symbols

UND_Stack_Size 00000400

Symbol: UND_Stack_Size
   Definitions
      At line 40 in file S3C2410A.s
   Uses
      At line 48 in file S3C2410A.s
      At line 1077 in file S3C2410A.s

UPLLCON_OFS 00000008

Symbol: UPLLCON_OFS
   Definitions
      At line 78 in file S3C2410A.s
   Uses
      At line 992 in file S3C2410A.s
Comment: UPLLCON_OFS used once
UPLLCON_Val 00028080

Symbol: UPLLCON_Val
   Definitions
      At line 149 in file S3C2410A.s
   Uses
      At line 934 in file S3C2410A.s
Comment: UPLLCON_Val used once
USR_Stack_Size 00001000

Symbol: USR_Stack_Size
   Definitions
      At line 45 in file S3C2410A.s
   Uses
      At line 48 in file S3C2410A.s
      At line 1121 in file S3C2410A.s

WTCNT_OFS 00000008

Symbol: WTCNT_OFS
   Definitions
      At line 172 in file S3C2410A.s
   Uses
      At line 972 in file S3C2410A.s
Comment: WTCNT_OFS used once
WTCON_OFS 00000000

Symbol: WTCON_OFS
   Definitions
      At line 170 in file S3C2410A.s
   Uses
      At line 974 in file S3C2410A.s
Comment: WTCON_OFS used once
WTCON_Val 00000000

Symbol: WTCON_Val
   Definitions
      At line 185 in file S3C2410A.s
   Uses
      At line 970 in file S3C2410A.s
Comment: WTCON_Val used once
WTDAT_OFS 00000004



ARM Macro Assembler    Page 21 Alphabetic symbol ordering
Absolute symbols


Symbol: WTDAT_OFS
   Definitions
      At line 171 in file S3C2410A.s
   Uses
      At line 973 in file S3C2410A.s
Comment: WTDAT_OFS used once
WTDAT_Val FFFF8000

Symbol: WTDAT_Val
   Definitions
      At line 186 in file S3C2410A.s
   Uses
      At line 971 in file S3C2410A.s
Comment: WTDAT_Val used once
WT_BASE 53000000

Symbol: WT_BASE
   Definitions
      At line 169 in file S3C2410A.s
   Uses
      At line 969 in file S3C2410A.s
Comment: WT_BASE used once
WT_SETUP 00000001

Symbol: WT_SETUP
   Definitions
      At line 184 in file S3C2410A.s
   Uses
      At line 968 in file S3C2410A.s
Comment: WT_SETUP used once
145 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
External symbols

__main 00000000

Symbol: __main
   Definitions
      At line 1107 in file S3C2410A.s
   Uses
      At line 1110 in file S3C2410A.s
Comment: __main used once
__use_two_region_memory 00000000

Symbol: __use_two_region_memory
   Definitions
      At line 1116 in file S3C2410A.s
   Uses
      None
Comment: __use_two_region_memory unused
2 symbols
502 symbols in table
